SEMICONDUCTOR PACKAGE HAVING REDUCED PARASITIC INDUCTANCE
Granted: March 21, 2024
Application Number:
20240096768
A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly…
SEMICONDUCTOR PACKAGE HAVING SMART POWER STAGE AND E-FUSE SOLUTION
Granted: December 28, 2023
Application Number:
20230420362
A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch…
SEMICONDUCTOR PACKAGE HAVING WETTABLE LEAD FLANKS AND TIE BARS AND METHOD OF MAKING THE SAME
Granted: December 28, 2023
Application Number:
20230420340
A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie…
POWER CONVERTER FOR HIGH POWER DENSITY APPLICATIONS
Granted: December 21, 2023
Application Number:
20230412070
A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is…
SEMICONDUCTOR POWER MODULE PACKAGE HAVING LEAD FRAME ANCHORED BARS
Granted: October 19, 2023
Application Number:
20230335474
A power module includes a lead frame, a substrate mounted on the lead frame, a first anchor pad, a second anchor pad, a plurality of die pads, and a plurality of transistor dies. The lead frame includes a first lead frame anchored bar attached to the first anchor pad, and a second lead frame anchored bar attached to the second anchor pad. The power module may include a single control IC or two or more control ICs. For the case including a single control IC, the singe control IC controls…
CIRCUIT AND METHOD FOR CONTROLLING SWITCHING REGULATOR WITH ULTRASONIC MODE
Granted: September 28, 2023
Application Number:
20230308018
A control circuit for controlling a switching regulator includes a timer, a comparator, a driver circuit and a controller. The timer generates an input signal indicative of whether a predetermined amount of time has elapsed since an activation of a drive signal. The comparator is configured to compare a feedback voltage with a reference voltage to generate a comparison signal. The driver circuit is controlled by a control signal to generate the drive signal according to one of the input…
CHIP SCALE PACKAGE (CSP) SEMICONDUCTOR DEVICE HAVING THIN SUBSTRATE
Granted: September 28, 2023
Application Number:
20230307325
A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 ?m to 35 ?m. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger…
INTELLIGENT POWER MODULE CONTAINING EXPOSED SURFACES OF TRANSISTOR DIE SUPPORTING ELEMENTS
Granted: September 7, 2023
Application Number:
20230282554
An intelligent power module (IPM) comprises a first transistor die supporting element, a second transistor die supporting element, a third transistor die supporting element, and a fourth transistor die supporting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a tie bar, a low voltage IC, a high voltage IC, a plurality of leads, a first slanted section, a second slanted section, a third slanted section, a…
High Bandwidth Constant On-Time PWM Control
Granted: August 10, 2023
Application Number:
20230253870
Apparatus and associated methods relate to dynamic bandwidth control of a variable frequency modulation circuit by selective contribution of a crossover frequency tuning engine (XFTE) in response to a transient in a switching frequency. In an illustrative example, the XFTE may generate a transient control signal (Ctrans) in response to a transient in a control output signal (Cout) indicative of switching frequency and received from a feedback control circuit. The XFTE may generate…
SEMICONDUCTOR PACKAGE HAVING MOLD LOCKING FEATURE
Granted: July 6, 2023
Application Number:
20230215783
A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be…
POWER CONVERTER FOR HIGH POWER DENSITY APPLICATIONS
Granted: May 4, 2023
Application Number:
20230137176
A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is…
POWER CONVERTER FOR HIGH POWER DENSITY APPLICATIONS
Granted: May 4, 2023
Application Number:
20230137176
A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is…
SEMICONDUCTOR PACKAGE HAVING THIN SUBSTRATE AND METHOD OF MAKING THE SAME
Granted: January 26, 2023
Application Number:
20230021687
A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of…
SEMICONDUCTOR PACKAGE HAVING THIN SUBSTRATE AND METHOD OF MAKING THE SAME
Granted: January 26, 2023
Application Number:
20230021687
A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of…
FLYBACK CONVERTER FOR CONTROLLING ON TIME VARIATION
Granted: December 8, 2022
Application Number:
20220393600
A flyback converter to control conduction time in AC/DC conversion technology. The flyback converter includes a primary side and a secondary side. The primary side includes a main switch connecting a primary coil to the input of the flyback converter in series. The secondary side includes a secondary coil coupling with the output terminal of the flyback converter. When a switching frequency of the main switch is at a preset first on time in the range between the off frequency and the…
NOISE DISTURBANCE REJECTION FOR POWER SUPPLY
Granted: November 3, 2022
Application Number:
20220352881
Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for…
ISOLATED CONVERTER WITH CONSTANT VOLTAGE MODE AND CONSTANT CURRENT MODE AND CONTROL METHOD THEREOF
Granted: March 31, 2022
Application Number:
20220103076
An isolated converter has a constant voltage mode and a constant current mode. The isolated converter includes a transformer, a main switch, a driver, a controller, and an isolator. The controller includes a constant current control unit, a voltage comparator, and a control logic unit. The constant current control unit generates a voltage adjustment signal to adjust the reference voltage or voltage feedback signal according to a current feedback signal for sensing the output current. The…
SEMICONDUCTOR PACKAGE HAVING ENLARGED GATE PAD AND METHOD OF MAKING THE SAME
Granted: December 23, 2021
Application Number:
20210398926
A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact…
FLYBACK CONVERTER AND CONTROL METHOD THEREOF
Granted: November 25, 2021
Application Number:
20210367523
A flyback converter, including: a transformer, a first switch, a second switch, and a control circuit. The transformer includes a first side and a second side. The first switch is coupled to the first side at an input terminal. The second switch is coupled to the second side and an output terminal. The control circuit is coupled between the output terminal and the second switch, wherein the control circuit is arranged to adjust a voltage on the input terminal by changing a flow of a…
FLYBACK CONVERTER, CONTROL CIRCUIT THEREOF, AND ASSOCIATED CONTROL METHOD
Granted: November 11, 2021
Application Number:
20210351702
A flyback converter includes a transformer, a sensing impedance, a switch and a control circuit. The sensing impedance is coupled between the transformer and an output terminal of the flyback converter. The switch is coupled to the transformer. The transformer is charged when the switch activates. The transformer is discharged when the switch deactivates. The control circuit is arranged to detect if the sensing impedance is bypassed, and further arranged to adjust an operating frequency…
