Alpha & Omega Semiconductor Patent Grants

Method and circuit for detecting short circuit in an asynchronous DC-DC boost converter

Granted: June 20, 2017
Patent Number: 9684326
A simple, cost-effective and efficient short circuit protection with simple routing of the ground on the PCB is achieved in an asynchronous DC-DC boost converter wherein a voltage sensing controller selectively isolates an input power supply to a load in the event of a short circuit. The controller alleviates need for additional components by utilizing the circuit for under voltage lockout protection and the circuit for overvoltage protection to generate signals for detecting short…

Embedded package and method thereof

Granted: June 20, 2017
Patent Number: 9685430
A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of…

Integrated snubber in a single poly MOSFET

Granted: June 20, 2017
Patent Number: 9685435
Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

Compact guard ring structure for CMOS integrated circuits

Granted: June 20, 2017
Patent Number: 9685443
An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring of the second conductivity type formed in the semiconductor layer surrounding the first guard ring and the active device and including comprising alternating first well regions of the first conductivity type and the second well…

Diode structures with controlled injection efficiency for fast switching

Granted: June 20, 2017
Patent Number: 9685523
This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type…

Circuit and method for evaluation overload condition in flyback converter

Granted: June 20, 2017
Patent Number: 9685874
A circuit and a method for evaluating a load condition in a flyback converter are disclosed. A first current source is used for providing a preset current ISUM equal to a sum of the off current value IOFF and the blanking current value ILEB to charge a first capacitor, and a second current source is used for providing a reference current IREF to charge a second capacitor. A comparator receives a voltage applied on the first capacitor at its positive input end and a voltage applied on the…

Method for monitoring epitaxial growth geometry shift

Granted: June 13, 2017
Patent Number: 9679822
A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer is grown. The epitaxial layer covers the first trenches and the second trenches but not the third trenches. First and second recesses on a top surface of the epitaxial layer are formed. First and second openings aligned with the first and the second recesses and a third openings aligned with the third trenches are formed in a…

Semiconductor package with small gate clip and assembly method

Granted: June 13, 2017
Patent Number: 9679833
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted…

Dual oxide trench gate power MOSFET using oxide filled trench

Granted: June 6, 2017
Patent Number: 9673289
A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a…

Methods and devices for detecting the input voltage and discharging the residuevoltage

Granted: May 30, 2017
Patent Number: 9664714
The present invention relates to power conversion systems, specifically, it relates to a device for detecting the DC voltage rectified from the AC power supply voltage in an AC-DC converter, primarily used to determine whether the DC input voltage is under a brown-out level and to monitor whether the AC power supply is removed and to discharge the residue DC voltage generated in a high frequency filter capacitor, which is used to filter high frequency noise signals of the AC power…

Dual-gate trench IGBT with buried floating P-type shield

Granted: May 30, 2017
Patent Number: 9666666
A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate;…

Semiconductor device with thick bottom metal and preparation method thereof

Granted: May 16, 2017
Patent Number: 9653383
A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method

Granted: May 16, 2017
Patent Number: 9653424
This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size,…

Power semiconductor device with small contact footprint and the preparation method

Granted: May 9, 2017
Patent Number: 9646920
A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor…

Manufacturing methods for accurately aligned and self-balanced superjunction devices

Granted: May 9, 2017
Patent Number: 9647059
This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a…

Closed cell configuration to increase channel density for sub-micron planar semiconductor power device

Granted: May 9, 2017
Patent Number: 9647078
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a…

Assymetric poly gate for optimum termination design in trench power MOSFETs

Granted: April 18, 2017
Patent Number: 9627526
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Circuit suppressing excessive current in startup phase of a voltage converter and method thereof

Granted: April 18, 2017
Patent Number: 9627983
A control circuit and the control method for controlling the current voltage converter of a power conversion system in the start-up phase are disclosed. A first voltage is applied to the non-inverting input terminal of the comparator and a reference voltage is applied to the inverting input terminal of the comparator. When the first voltage exceeds the reference voltage, the comparison result from the comparator triggers the frequency of the clock signal generated by the oscillator to…

Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection

Granted: April 11, 2017
Patent Number: 9620498
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns…

Integrated Schottky diode in high voltage semiconductor device

Granted: April 11, 2017
Patent Number: 9620584
This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide…