Alpha & Omega Semiconductor Patent Grants

Semiconductor device with thick bottom metal and preparation method thereof

Granted: May 16, 2017
Patent Number: 9653383
A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method

Granted: May 16, 2017
Patent Number: 9653424
This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size,…

Power semiconductor device with small contact footprint and the preparation method

Granted: May 9, 2017
Patent Number: 9646920
A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor…

Manufacturing methods for accurately aligned and self-balanced superjunction devices

Granted: May 9, 2017
Patent Number: 9647059
This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a…

Closed cell configuration to increase channel density for sub-micron planar semiconductor power device

Granted: May 9, 2017
Patent Number: 9647078
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a…

Assymetric poly gate for optimum termination design in trench power MOSFETs

Granted: April 18, 2017
Patent Number: 9627526
A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Circuit suppressing excessive current in startup phase of a voltage converter and method thereof

Granted: April 18, 2017
Patent Number: 9627983
A control circuit and the control method for controlling the current voltage converter of a power conversion system in the start-up phase are disclosed. A first voltage is applied to the non-inverting input terminal of the comparator and a reference voltage is applied to the inverting input terminal of the comparator. When the first voltage exceeds the reference voltage, the comparison result from the comparator triggers the frequency of the clock signal generated by the oscillator to…

Injection control in semiconductor power devices

Granted: April 11, 2017
Patent Number: 9620630
Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first…

Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection

Granted: April 11, 2017
Patent Number: 9620498
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns…

Integrated Schottky diode in high voltage semiconductor device

Granted: April 11, 2017
Patent Number: 9620584
This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide…

Sawtooth electric field drift region structure for power semiconductor devices

Granted: April 11, 2017
Patent Number: 9620614
This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch…

Semiconductor device employing trenches for active gate and isolation

Granted: March 14, 2017
Patent Number: 9595517
A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device formed in the semiconductor layer adjacent the first trench. The second trench encircles active area of the first transistor device to provide electrical…

Split poly connection via through-poly-contact (TPC) in split-gate based power MOSFETs

Granted: March 14, 2017
Patent Number: 9595587
Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top…

Semiconductor device including superjunction structure formed using angled implant process

Granted: March 14, 2017
Patent Number: 9595609
A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown…

Transient voltage suppressor (TVS) with reduced breakdown voltage

Granted: February 28, 2017
Patent Number: 9583586
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and…

Termination design for high voltage device

Granted: February 21, 2017
Patent Number: 9577072
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the…

Voltage control method and apparatus for achieving and maintaining a targeted voltage on a load

Granted: February 21, 2017
Patent Number: 9577518
The present invention discloses a voltage control method. First, the load voltage of the load is divided to generate a feedback voltage. Then, an absolute value of a periodic triangular wave signal is retrieved to generate a positive feedback signal, which and the feedback voltage are then combined to produce a sum signal. The sum signal is then compared with a target voltage and when the sum signal is less than the target voltage, a control signal is generated and thus the load voltage…

Constant on-time (COT) control in isolated converter

Granted: February 21, 2017
Patent Number: 9577542
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…

Constant on time (COT) control in isolated converter

Granted: February 21, 2017
Patent Number: 9577543
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…

Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application

Granted: February 14, 2017
Patent Number: 9570404
A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting…