Alpha & Omega Semiconductor Patent Grants

Compact CMOS device isolation

Granted: January 17, 2017
Patent Number: 9548307
An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and…

Semiconductor device with field threshold MOSFET for high voltage termination

Granted: January 17, 2017
Patent Number: 9548352
This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold…

Constant on-time (COT) control in isolated converter

Granted: January 17, 2017
Patent Number: 9548667
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…

Field effect transistor with integrated Zener diode

Granted: January 10, 2017
Patent Number: 9543292
One or more Zener diodes and a field effect transistor having a drain connected in series with the one or more Zener diodes are integrally formed by a plurality of doped regions in the same P-type semiconductor substrate and separated by a punch through stop region. An N-type region is formed under the one or more Zener diodes.

Corner layout for high voltage semiconductor devices

Granted: January 10, 2017
Patent Number: 9543413
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform…

Normally on high voltage switch

Granted: December 27, 2016
Patent Number: 9530885
In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to…

Wafer process for molded chip scale package (MCSP) with thick backside metallization

Granted: December 13, 2016
Patent Number: 9520380
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a…

Configuration and method to generate saddle junction electric field in edge termination

Granted: December 13, 2016
Patent Number: 9520464
This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

Normally off gallium nitride field effect transistors (FET)

Granted: December 13, 2016
Patent Number: 9520480
A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction…

Voltage detection circuit and a method of detecting voltage changes

Granted: December 6, 2016
Patent Number: 9515570
A power conversion system and a method for voltage change detection, specifically, relates to a detection circuit implemented in the AC-DC power converter, detect the voltage change. The AC input voltage is rectified to convert into a DC input voltage transmitted to a detection unit generating a detection voltage signal at different logical states corresponding to the input voltage changes. A charge current source unit is used for charging the capacitor when the detection voltage signal…

Termination design for nanotube MOSFET

Granted: November 29, 2016
Patent Number: 9508805
A termination structure for a semiconductor power device includes a plurality of termination groups formed in a lightly doped epitaxial layer of a first conductivity type over a heavily doped semiconductor substrate of a second conductivity type. Each termination group includes a trench formed in the lightly doped epitaxial layer of the first conductivity type. All sidewalls of the trench are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two…

Method and structure for wafer level packaging with large contact area

Granted: November 22, 2016
Patent Number: 9502268
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…

Nanotube semiconductor devices

Granted: November 22, 2016
Patent Number: 9502503
Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and…

Charge reservoir IGBT top structure

Granted: November 22, 2016
Patent Number: 9502547
An IGBT device may be formed from a substrate including a bottom semiconductor layer of a first conductivity and an upper semiconductor layer of a second conductivity type located above the bottom semiconductor layer. Trenches for trench gates are formed in the substrate. Each trench extends vertically into the upper semiconductor layer and is provided with a gate insulator on each side of the trench and is filled with polysilicon. A first conductivity type floating body region is formed…

High frequency switching MOSFETs with low output capacitance using a depletable P-shield

Granted: November 22, 2016
Patent Number: 9502554
Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an…

Flyback converter output current evaluation circuit and evaluation method

Granted: November 8, 2016
Patent Number: 9490712
An output current calculating circuit for a flyback converter operating under CCM and DCM is disclosed. The off current value ION and the blanking current value ILEB flowing through a sensing resistor are calculated using a detection module and are summed together using a current summing unit. A voltage converted from the sum value of the off current value IOFF and the blanking current value ILEB is transmitted through an output stage in a predetermined time ratio of a cycle with the…

Compact duty modulator

Granted: November 8, 2016
Patent Number: 9491014
Switching logic receives an input signal and a frequency divided signal and generates switching signals. A delay modulator receives the switching signals and generates a high output when a first node voltage is greater than a second node voltage and low output otherwise. An XOR gate receives the delay modulator's output and the frequency divided signal and produces a final output that is high when one of them is low and the other high and low otherwise. A duty ratio of the final output…

Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs

Granted: November 1, 2016
Patent Number: 9484452
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a…

Device structure and methods of making high density MOSFETs for load switch and DC-DC applications

Granted: November 1, 2016
Patent Number: 9484453
Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of…

Methods for fabricating anode shorted field stop insulated gate bipolar transistor

Granted: October 25, 2016
Patent Number: 9478646
A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.