Alpha & Omega Semiconductor Patent Grants

Semiconductor device employing trenches for active gate and isolation

Granted: March 14, 2017
Patent Number: 9595517
A semiconductor device includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer including a first trench gate; a second trench formed in the semiconductor layer and extending into the substrate and including a second trench gate; a first transistor device formed in the semiconductor layer adjacent the first trench. The second trench encircles active area of the first transistor device to provide electrical…

Split poly connection via through-poly-contact (TPC) in split-gate based power MOSFETs

Granted: March 14, 2017
Patent Number: 9595587
Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top…

Semiconductor device including superjunction structure formed using angled implant process

Granted: March 14, 2017
Patent Number: 9595609
A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown…

Transient voltage suppressor (TVS) with reduced breakdown voltage

Granted: February 28, 2017
Patent Number: 9583586
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and…

Termination design for high voltage device

Granted: February 21, 2017
Patent Number: 9577072
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the…

Voltage control method and apparatus for achieving and maintaining a targeted voltage on a load

Granted: February 21, 2017
Patent Number: 9577518
The present invention discloses a voltage control method. First, the load voltage of the load is divided to generate a feedback voltage. Then, an absolute value of a periodic triangular wave signal is retrieved to generate a positive feedback signal, which and the feedback voltage are then combined to produce a sum signal. The sum signal is then compared with a target voltage and when the sum signal is less than the target voltage, a control signal is generated and thus the load voltage…

Constant on-time (COT) control in isolated converter

Granted: February 21, 2017
Patent Number: 9577542
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…

Constant on time (COT) control in isolated converter

Granted: February 21, 2017
Patent Number: 9577543
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…

Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application

Granted: February 14, 2017
Patent Number: 9570404
A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting…

Battery protection package and process of making the same

Granted: February 7, 2017
Patent Number: 9564406
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and…

Method of making integrated MOSFET-schottky diode device with reduced source and body kelvin contact impedance and breakdown voltage

Granted: February 7, 2017
Patent Number: 9564516
A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned…

Fabrication of shielded gate trench MOSFET with increased source-metal contact

Granted: January 31, 2017
Patent Number: 9559179
A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a gate top dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region; a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source…

Compact CMOS device isolation

Granted: January 17, 2017
Patent Number: 9548307
An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and…

Semiconductor device with field threshold MOSFET for high voltage termination

Granted: January 17, 2017
Patent Number: 9548352
This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold…

Constant on-time (COT) control in isolated converter

Granted: January 17, 2017
Patent Number: 9548667
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…

Field effect transistor with integrated Zener diode

Granted: January 10, 2017
Patent Number: 9543292
One or more Zener diodes and a field effect transistor having a drain connected in series with the one or more Zener diodes are integrally formed by a plurality of doped regions in the same P-type semiconductor substrate and separated by a punch through stop region. An N-type region is formed under the one or more Zener diodes.

Corner layout for high voltage semiconductor devices

Granted: January 10, 2017
Patent Number: 9543413
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform…

Normally on high voltage switch

Granted: December 27, 2016
Patent Number: 9530885
In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to…

Wafer process for molded chip scale package (MCSP) with thick backside metallization

Granted: December 13, 2016
Patent Number: 9520380
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a…

Configuration and method to generate saddle junction electric field in edge termination

Granted: December 13, 2016
Patent Number: 9520464
This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.