Altera Patent Applications

INTEGRATED CIRCUIT PACKAGES WITH DETACHABLE INTERCONNECT STRUCTURES

Granted: April 27, 2017
Application Number: 20170117250
An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order to establish electrical communication between the first and second integrated circuit dies, the first conductive structure of the detachable interconnect…

STATE VISIBILITY AND MANIPULATION IN INTEGRATED CIRCUITS

Granted: April 13, 2017
Application Number: 20170103157
In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an…

MULTI-LEVEL SIGNALING FOR ON-PACKAGE CHIP-TO-CHIP INTERCONNECT THROUGH SILICON BRIDGE

Granted: March 30, 2017
Application Number: 20170092586
One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is…

Techniques For Variable Forward Error Correction

Granted: December 22, 2016
Application Number: 20160373138
A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a…

PHASE DETECTION IN AN ANALOG CLOCK DATA RECOVERY CIRCUIT WITH DECISION FEEDBACK EQUALIZATION

Granted: December 22, 2016
Application Number: 20160373241
An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the…

Techniques For Providing Data Rate Changes

Granted: December 15, 2016
Application Number: 20160363954
An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate…

N-WELL/P-WELL STRAP STRUCTURES

Granted: December 8, 2016
Application Number: 20160358825
Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

ASYMMETRIC POWER FLOW CONTROLLER FOR A POWER CONVERTER AND METHOD OF OPERATING THE SAME

Granted: October 20, 2016
Application Number: 20160308440
A controller for a power converter formed with a plurality of converter stages, and method of operating the same. In one embodiment, the controller includes a power system controller configured to determine an unequal current allocation among the plurality of converter stages based on an operation of the power converter. The controller also includes a converter stage controller configured to control an output current produced by each of the plurality of converter stages in response to…

METHODS AND APPARATUS FOR TWO-DIMENSIONAL BLOCK BIT-STREAM COMPRESSION AND DECOMPRESSION

Granted: September 1, 2016
Application Number: 20160253096
One embodiment relates to a method for compressing a data-stream of configuration data for electronically configuring an electronically-programmable semiconductor device having a two-dimensional (2D) block structure for an array of core resources. Inter-block and intra-block transformations may be applied to the data-stream to obtain a 2D-transformed data-stream which can be shorter and/or more compressible than the original data. Subsequently, one-dimensional (1D) compression that…

PACKAGED INTEGRATED CIRCUIT INCLUDING A SWITCH-MODE REGULATOR AND METHOD OF FORMING THE SAME

Granted: September 1, 2016
Application Number: 20160254745
A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.

CAPACITOR OF VARIABLE CAPACITY, COMPRISING A LAYER OF A PHASE CHANGE MATERIAL, AND METHOD FOR VARYING THE CAPACITY OF A CAPACITOR

Granted: June 16, 2016
Application Number: 20160172113
The invention relates to a variable-capacitance electrical capacitor comprising a first electrode and a second electrode facing the first electrode and a zone of a dielectric material arranged between said first and second electrodes characterized in that the second electrode is formed at least on one hand of a primary electrode made of an electrically conductive material and, at least on the other, of an additional electrode comprising a state-change material, the primary electrode and…

METHODS AND APPARATUS FOR AUTOMATIC FAULT DETECTION

Granted: April 28, 2016
Application Number: 20160116536
Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates…

ROUTING AND PROGRAMMING FOR RESISTIVE SWITCH ARRAYS

Granted: February 11, 2016
Application Number: 20160043724
Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of…

System Reset Controller Replacing Individual Asynchronous Resets

Granted: October 15, 2015
Application Number: 20150295579
An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no…

MULTI-RATE TRANSCEIVER CIRCUITRY

Granted: October 8, 2015
Application Number: 20150288511
Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data…

INTEGRATED CURRENT REPLICATOR AND METHOD OF OPERATING THE SAME

Granted: October 1, 2015
Application Number: 20150280558
An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power…

APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT

Granted: October 1, 2015
Application Number: 20150281031
One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write…

SILICON-GLASS HYBRID INTERPOSER CIRCUITRY

Granted: August 20, 2015
Application Number: 20150235921
An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be…

METHODS FOR PACKAGING INTEGRATED CIRCUITS

Granted: August 13, 2015
Application Number: 20150228506
Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively…

CONFIGURATION BIT ARCHITECTURE FOR PROGRAMMABLE INTEGRATED CIRCUIT DEVICE

Granted: July 30, 2015
Application Number: 20150214229
An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one…