Altera Patent Grants

Invariant code optimization in high-level FPGA synthesis

Granted: January 17, 2017
Patent Number: 9547738
A method of programming or configuring an integrated circuit device using a high-level language includes parsing a logic flow to be embodied in the integrated circuit device to identify invariant logic flow, converting the invariant logic flow into separate instruction blocks, incorporating the separate instruction blocks into a high-level language representation of a configuration of resources of the integrated circuit device, and compiling the high-level language representation to…

Segment-based encoding system including segment-specific metadata

Granted: January 17, 2017
Patent Number: 9547916
An encoder segments frames of video data and associates metadata with segments. The metadata elements can be associated with the segments that include areas of the frame associated with the metadata elements. A motion matcher can match segments of a reference frame to pixels of a current nonkey frame being encoded when a metadata associator associates elements of metadata with segments of the segmentation of the reference frame and associates a matched segment's metadata elements with…

Scaleable look-up table based memory

Granted: January 17, 2017
Patent Number: 9548103
An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block…

Methods and apparatus for passive equalization in high-speed and high density integrated circuits

Granted: January 17, 2017
Patent Number: 9548278
A passive equalization structure is provided. The passive equalization structure includes a semiconductor substrate having first and a differential pair having first and second signal conductors. The first signal conductor is formed in a first layer of the semiconductor substrate. The second signal conductor is formed in a second layer in the semiconductor substrate that is different than the first layer. The passive equalization structure further includes first and second reference…

Power converter with a dynamically configurable controller and output filter

Granted: January 17, 2017
Patent Number: 9548714
A controller and an output filter for a power converter, and a power converter employing at least one of the same. In one embodiment, the controller includes an error amplifier with first and second input terminals coupled to one of an operating characteristic and a reference voltage of the power converter, and a switch configured to couple the first and second input terminals to one of the operating characteristic and the reference voltage as a function of a power conversion mode of the…

Multiple alternate configurations for an integrated circuit device

Granted: January 17, 2017
Patent Number: 9548740
A method of configuring an integrated circuit device to perform a function includes storing a plurality of configurations for performing the function, each of the configurations being designed for a different characteristic of a particular input to the function. Inputs are received for the function, including the particular input. The characteristic of the particular input as received is examined, and one of the plurality of configurations is instantiated based on that characteristic of…

IC and a method for flexible integer and fractional divisions

Granted: January 17, 2017
Patent Number: 9548743
An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that…

FinFET with improved SEU performance

Granted: January 10, 2017
Patent Number: 9543382
Illustratively, a finFET comprises at least one fin, and typically several fins, with a trapping region in or on a substrate at the base of each fin to trap ions produced by radiation incident on the substrate. In one embodiment, the trapping region is an implanted region having a conductivity type opposite that of the substrate. In another, the trapping region is a defect region. In another, the trapping region is an epitaxial region grown on the substrate. The finFET is formed by…

Interposer with embedded clock network circuitry

Granted: January 10, 2017
Patent Number: 9543965
An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second…

Apparatus for improved communication and associated methods

Granted: January 10, 2017
Patent Number: 9544092
An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link.

Method and apparatus for performing parallel routing using a multi-threaded routing procedure

Granted: January 3, 2017
Patent Number: 9536034
A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Power distribution network

Granted: January 3, 2017
Patent Number: 9536820
An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling…

Semiconductor device including a resistor metallic layer and method of forming the same

Granted: January 3, 2017
Patent Number: 9536938
A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a…

Apparatus for configurable interface and associated methods

Granted: January 3, 2017
Patent Number: 9537488
An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.

Multimode equalization circuitry

Granted: January 3, 2017
Patent Number: 9537681
An integrated circuit may include receiver circuitry that receives data from an external device. Such receiver circuitry may include, among other things, equalization circuitry that may reconstruct the received data before transmitting the received data to other parts of the integrated circuit. The receiver circuitry may include two different equalization circuits. A first equalization circuit may perform equalization on the received data to generate a first equalized output while a…

Register retiming and verification of an integrated circuit design

Granted: December 27, 2016
Patent Number: 9529947
A circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the circuit design description, whereby registers are moved across combinational gates, information about the register moves are recorded, and ultimately a modified circuit design description is created. The circuit design computing equipment may perform sequential equivalence checking to ensure that the circuit design description and the modified…

Systems and methods for performing profile-based circuit optimization using high-level system modeling

Granted: December 27, 2016
Patent Number: 9529950
Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when…

Integrated circuits with guard ring structures for nonplanar transistor devices

Granted: December 27, 2016
Patent Number: 9530835
Integrated circuits with guard rings are provided. Integrated circuits may include functional circuitry that is sensitive to random noise sources. The functional circuitry may be formed using nonplanar transistor devices such as FinFET devices. A nonplanar guard ring may be provided that help isolate the functional circuitry from the interfering noise sources. The nonplanar guard ring may include edges that are formed using long rectangular strips of diffusion regions and/or smaller…

Techniques for generating clock signals using oscillators

Granted: December 27, 2016
Patent Number: 9531390
An integrated circuit includes first and second data channel circuits and first and second inductor-capacitor (LC) tank oscillator circuits. The first data channel circuit generates a first data signal in response to a first clock signal. The second data channel circuit generates a second data signal in response to a second clock signal. The frequencies of the first and second clock signals are substantially the same. The first LC tank oscillator circuit generates a first periodic…

Multi-protocol configurable transceiver including configurable deskew in an integrated circuit

Granted: December 27, 2016
Patent Number: 9531646
Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an…