Altera Patent Grants

Integrated circuit (IC) with primary and secondary networks and device containing such an IC

Granted: March 28, 2017
Patent Number: 9606176
Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary…

Configurable clock grid structures

Granted: March 28, 2017
Patent Number: 9606573
Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second…

Low power optimizations for a floating point multiplier

Granted: March 28, 2017
Patent Number: 9606608
Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device…

Programmable integrated circuits with in-operation reconfiguration capability

Granted: March 28, 2017
Patent Number: 9607671
Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In…

Integrated circuit package with vacant cavity

Granted: March 28, 2017
Patent Number: 9607863
Integrated circuit packages with cavity are disclosed. A disclosed integrated circuit package includes a first die. A second die may be coupled to the first die by attaching the first die to a top surface of the second die. A blocking element such as a barrier structure may be formed that surrounds the second die. A cavity may be formed between the blocking element and the first die that encloses the second die. The barrier structure may help prevent underfill material from entering the…

Integrated circuit device with field programmable optical array

Granted: March 28, 2017
Patent Number: 9608728
Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical…

Programmable device using fixed and configurable logic to implement recursive trees

Granted: March 21, 2017
Patent Number: 9600278
A specialized processing block on a programmable integrated circuit device includes a first floating-point arithmetic operator stage, and a floating-point adder stage having at least one floating-point binary adder. Configurable interconnect within the specialized processing block routes signals into and out of each of the first floating-point arithmetic operator stage and the floating-point adder stage. The block has a plurality of block inputs, at least one block output, a…

Secure boot using a field programmable gate array (FPGA)

Granted: March 21, 2017
Patent Number: 9600291
This disclosure describes techniques for ensuring security in an integrated circuit system that includes a processor subsystem and a configurable-logic (e.g., FPGA) subsystem, which is capable of storing code executed by the processor. Techniques for utilizing the configurable-logic to control the process of booting a processor in the processor subsystem securely are described. Because the configurable-logic may be on the same die as the processor in the integrated circuit, the…

Error detection and correction circuitry

Granted: March 21, 2017
Patent Number: 9600366
Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize…

Apparatus and methods for optimization of integrated circuits

Granted: March 21, 2017
Patent Number: 9600622
A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Methods and circuitry for identifying logic regions affected by soft errors

Granted: March 21, 2017
Patent Number: 9601217
Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the…

Stacked leadframe packages

Granted: March 21, 2017
Patent Number: 9601419
A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package. The first package may be a leadframe package that includes metal leads extending beyond the perimeter of the first package. The first package may include a first integrated circuit die assembled within the first package using the wirebond configuration or the flip-chip configuration. The second package may be a leadframe package or…

Methods for optimizing circuit performance via configurable clock skews

Granted: March 21, 2017
Patent Number: 9602106
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and…

Multiple plane network-on-chip with master/slave inter-relationships

Granted: March 21, 2017
Patent Number: 9602587
Systems and methods are provided herein for implementing a Network-on-Chip (NoC) in a System-on-Chip (SoC) device. In some embodiments, an NoC may include a first node that transmits data to a second node, where data may be transmitted via either a first plane or a second plane. The first plane may utilize first logic at each of an output port of the first node, an input port of the second node, and at intermediary ports when transmitting the data to the second node. The second plane may…

Cache debug system for programmable circuits

Granted: March 14, 2017
Patent Number: 9594655
An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the…

Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements

Granted: March 14, 2017
Patent Number: 9594723
An adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.…

Apparatus and associated methods for parallelizing clustering and placement

Granted: March 14, 2017
Patent Number: 9594859
A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.

Multi-channel, multi-lane encryption circuitry and methods

Granted: March 14, 2017
Patent Number: 9594928
Encryption/authentication circuitry includes an encryption portion having a first number of encryption lanes, each encryption lane including a plurality of encryption stages, and keyspace circuitry including a plurality of key lanes corresponding to a predetermined maximum number of channels. Each key lane has key storage stages corresponding to the encryption stages, and includes key memories for the predetermined maximum number of channels. Key channel selection circuitry for each…

Multiple-die synchronous insertion delay measurement circuit and methods

Granted: March 14, 2017
Patent Number: 9595308
Circuitry and methods are disclosed for accurately measuring a latency of a data path through multiple FIFO buffers on separate semiconductor dies. A base latency of each FIFO may be measured by measuring an average occupancy of the FIFO. The base latency of each FIFO may then be adjusted using quantities measured using the circuitry and methods disclosed herein. These quantities may include: the phase delay difference between FIFO read and write clocks; and the insertion delay for the…

Adaptive refresh scheduling for memory

Granted: March 14, 2017
Patent Number: 9595312
The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence.…