Altera Patent Grants

Method and apparatus for performing register retiming in the presence of timing analysis exceptions

Granted: July 18, 2017
Patent Number: 9710591
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

On-die input reference voltage with self-calibrating duty cycle correction

Granted: July 18, 2017
Patent Number: 9711189
A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that…

Serial memory interface circuitry for programmable integrated circuits

Granted: July 18, 2017
Patent Number: 9712186
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet…

Self-stuffing multi-clock FIFO requiring no synchronizers

Granted: July 11, 2017
Patent Number: 9703526
An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers.…

Guided memory buffer allocation

Granted: July 11, 2017
Patent Number: 9703696
Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.

Secure physically unclonable function (PUF) error correction

Granted: July 11, 2017
Patent Number: 9703989
An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may be part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may differ from the desired PUF…

Power gated lookup table circuitry

Granted: July 11, 2017
Patent Number: 9705504
A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary…

Field programmable gate array with integrated application specific integrated circuit fabric

Granted: July 11, 2017
Patent Number: 9705506
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA…

Integrated circuit with continuously adaptive equalization circuitry

Granted: July 11, 2017
Patent Number: 9705708
An integrated circuit for supporting a high-speed communications link is provided. The integrated circuit may include equalization circuitry having a continuous time linear equalizer (CTLE) circuit, a decision feedback equalizer (DFE) circuit, and associated adaptation logic for controlling the CTLE circuit and the DFE circuit. The adaptation logic may include an error minimization adaptation circuit operable to generate at least a first post-cursor value, a signal amplitude detection…

Fixed-point and floating-point optimization

Granted: July 4, 2017
Patent Number: 9696991
Systems and methods for enhancing fixed-point operations, floating-point operations, or a combination thereof for programs implemented on an integrated circuit (IC) are provided. Portions of these operations may be shared among the operations. Accordingly, the embodiments described herein enhance these fixed-point operations, floating-point operations, or a combination thereof based upon these portions of the operations that may be shared.

Metastability-hardened synchronization circuit

Granted: July 4, 2017
Patent Number: 9697309
An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

State visibility and manipulation in integrated circuits

Granted: July 4, 2017
Patent Number: 9697318
In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an…

Apparatus for stacked electronic circuitry and associated methods

Granted: July 4, 2017
Patent Number: 9698123
An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

Variable gate width FinFET

Granted: July 4, 2017
Patent Number: 9698252
An improved FinFET has a gate structure on only a portion of the available surface on a fin, thereby providing a FinFET with a finer granularity width dimension. To form the FinFET, a first etch-resistant sacrificial layer and a second etch-resistant spacer layer are formed on the fin. The spacer layer is etched anisotropically to remove the spacer layer from the top and upper sidewalls of the fin while leaving the spacer layer on the lower sidewalls of the FinFET. A gate dielectric and…

Level-sensitive two-phase single-wire latch controllers without contention

Granted: July 4, 2017
Patent Number: 9698784
Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A…

Systems and methods for coalescing regions on a virtualized programmable logic device

Granted: July 4, 2017
Patent Number: 9698794
Systems and methods for coalescing regions on a virtualized programmable logic device are provided. A first function is configured on a first subregion on the virtualized programmable logic device. The first subregion may border an unused subregion on the programmable logic device. The first function operated on the first subregion is migrated to a second function operated on a second subregion on the virtualized programmable logic device by mapping a first set of bits configuring the…

Supporting pseudo open drain input/output standards in a programmable logic device

Granted: July 4, 2017
Patent Number: 9698795
Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

Method and apparatus for high-level programs with general control flow

Granted: June 27, 2017
Patent Number: 9690278
A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control…

Configuration via high speed serial link

Granted: June 27, 2017
Patent Number: 9690741
Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Safety features for high level design

Granted: June 27, 2017
Patent Number: 9690894
This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with…