Altera Patent Grants

Structures for LUT-based arithmetic in PLDs

Granted: May 23, 2017
Patent Number: 9658830
A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of…

Method for reconfiguring an erroneous memory frame in an integrated circuit

Granted: May 23, 2017
Patent Number: 9658920
A method of correcting a configuration memory frame may include identifying an erroneous memory frame in a plurality of memory frames in the integrated circuit. The erroneous memory frame may be identified with error detection circuitry on the integrated circuit. A portion of data stored in an off-chip memory module may be read with controller circuitry. The read data portion may correspond to the erroneous memory frame. The erroneous memory frame may thus be corrected by loading the…

Transport network

Granted: May 23, 2017
Patent Number: 9659124
Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

Methods and apparatus for implementing feedback loops

Granted: May 23, 2017
Patent Number: 9660624
Circuitry that efficiently implements loop functions in an integrated circuit is provided. The circuitry combines a feed-forward circuit with a feedback loop that includes a unit delay element in a feedback path. The feedback path may couple the output of a processing element to the input of the processing element. The processing element may implement a function that satisfies commutative, associative, and distributive properties. Combining the feedback loop with the feed-forward circuit…

Clock grid for integrated circuit

Granted: May 23, 2017
Patent Number: 9660630
Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Integrated circuits with improved register circuitry

Granted: May 23, 2017
Patent Number: 9660650
Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations…

Techniques for reducing skew between clock signals

Granted: May 23, 2017
Patent Number: 9660653
A skew reduction circuit includes a first delay circuit that delays a first clock signal to generate a second clock signal and a second delay circuit that delays a third clock signal to generate a fourth clock signal. The skew reduction circuit also includes a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals. The skew reduction circuit adjusts a delay of one…

High-speed serial data signal receiver circuitry

Granted: May 23, 2017
Patent Number: 9660846
Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups…

Detailed placement with search and repair

Granted: May 16, 2017
Patent Number: 9652576
A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design and uses a satisfiability solver to resolve placement violations. In some embodiments, the constraints include mathematical expressions that express timing requirements. The method in some embodiments converts the mathematical expressions into Boolean clauses and sends the clauses to a…

Hardened programmable devices

Granted: May 16, 2017
Patent Number: 9654109
Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom…

Phase-locked loop architecture and clock distribution system

Granted: May 16, 2017
Patent Number: 9654123
One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Another embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources.…

Hybrid architecture for signal processing and signal processing accelerator

Granted: May 9, 2017
Patent Number: 9647667
Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input signals from the FPGA. The array of network nodes controllably route the input signals to the array of SPAs.

Apparatus for flexible electronic interfaces and associated methods

Granted: May 9, 2017
Patent Number: 9647668
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

Coreless organic substrate

Granted: May 9, 2017
Patent Number: 9648728
A coreless organic substrate in which a mounting hole is formed near each corner of the substrate and is used during assembly processes to secure the substrate so as to prevent flexing.

Systems and methods for preventing data remanence in memory systems

Granted: May 9, 2017
Patent Number: 9646177
Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of…

LC tank circuitry with shielding structures

Granted: May 9, 2017
Patent Number: 9646759
An integrated circuit having a resonant circuit is provided. The resonant circuit may include an inductor and a capacitor coupled in parallel. The inductor may be formed in a dielectric stack on a semiconductor substrate. An inductor shielding structure may be interposed between the inductor and the semiconductor substrate in the dielectric stack. The inductor shielding structure may be a closed loop structure that is electrically floating. The inductor shielding structure may also be…

Differential input buffer circuits and methods

Granted: May 9, 2017
Patent Number: 9647663
An input buffer circuit that receives differential signals includes a first resistive path circuit, a second resistive path circuit and a feedback circuit. The first resistive path circuit may generate a first common mode voltage from the differential signals. The feedback circuit is coupled to the first resistive path circuit. The feedback circuit receives the first common mode voltage as an input. The second resistive path circuit includes a transistor circuit and a resistor formed in…

Floating-point adder circuitry

Granted: May 2, 2017
Patent Number: 9639326
An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point…

CRC circuits with extended cycles

Granted: May 2, 2017
Patent Number: 9639416
A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and…

Selectable reconfiguration for dynamically reconfigurable IP cores

Granted: April 25, 2017
Patent Number: 9633158
Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and…