Altera Patent Grants

Combined adder and pre-adder for high-radix multiplier circuit

Granted: June 20, 2017
Patent Number: 9684488
Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second…

Methods and apparatus for storing error correction information on a memory controller circuit

Granted: June 20, 2017
Patent Number: 9684559
A memory controller circuit is disclosed. The memory controller circuit is coupled to an external memory device. The memory controller circuit selectively generates error-correction information for a user input. The selection is based on whether the user input is one of predefined inputs. In order to facilitate that, the memory controller circuit includes a command processor circuit and a memory circuit. The error-correction information is stored within the memory circuit located within…

Apparatus and methods for multiple-channel direct memory access

Granted: June 20, 2017
Patent Number: 9684615
One embodiment relates to an integrated circuit for a multiple-channel direct memory access system. The integrated circuit includes multiple direct memory access (DMA) controllers, each one corresponding to a different DMA channel. A channelizer receives descriptors from the DMA controllers. Fragmentation circuits in the channelizer fragment descriptors to generate multiple sub-descriptors therefrom, and the sub-descriptors may be sorted into priority queues. Another embodiment relates…

Method and apparatus for performing timing analysis on calibrated paths

Granted: June 20, 2017
Patent Number: 9684742
A method for performing timing analysis on calibrated paths includes performing static timing analysis on the calibrated paths to obtain delay and margin information. The delay and margin information are utilized to emulate operations performed during calibration.

System reset controller replacing individual asynchronous resets

Granted: June 20, 2017
Patent Number: 9685957
An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no…

Circuits and methods for DQS autogating

Granted: June 13, 2017
Patent Number: 9679633
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in…

Integrated circuit package with active warpage control printed circuit board mount

Granted: June 13, 2017
Patent Number: 9679861
An integrated circuit package may include a package substrate having a surface, first interconnects of a first size that are arranged in a substantially circular shape that is centered on the surface of the package substrate, and second interconnects of a second size that is different from the first size, where the second interconnects are arranged in a ring shape on the surface of the package substrate. The ring shape of the second interconnects is concentric with the substantially…

Multi-access memory system and a method to manufacture the system

Granted: June 13, 2017
Patent Number: 9679871
A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of the first package where the first die communicates with the second die at a first data rate while the first die communicates with the IC at a second data rate. The first data rate is higher than the second data…

Circuits and methods for impedance calibration

Granted: June 13, 2017
Patent Number: 9680469
A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the…

Signal monitoring systems for resolving nyquist zone ambiguity

Granted: June 13, 2017
Patent Number: 9680493
A signal monitoring system includes a splitter circuit, a single-bit channel circuit, a multi-bit channel circuit, and a frequency processor circuit. The splitter circuit splits a first analog signal into second and third analog signals. The single-bit channel circuit samples the second analog signal at a sampling rate that is greater than or equal to a Nyquist rate of the second analog signal to generate a first digital signal. The multi-bit channel circuit under-samples the third…

Methods and apparatus for automated adaptation of transmitter equalizer tap settings

Granted: June 13, 2017
Patent Number: 9680675
One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next…

Integrated circuit with dynamically-adjustable buffer space for serial interface

Granted: June 13, 2017
Patent Number: 9680773
One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

Methods and apparatus for transforming, loading, and executing super-set instructions

Granted: June 6, 2017
Patent Number: 9672033
Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from…

Semiconductor device having mirror-symmetric terminals and methods of forming the same

Granted: June 6, 2017
Patent Number: 9673135
A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a…

Integrated circuit package with embedded passive structures

Granted: June 6, 2017
Patent Number: 9673173
An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive…

Semiconductor device including a resistor metallic layer and method of forming the same

Granted: June 6, 2017
Patent Number: 9673192
A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a power switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the power switch. The resistor metallic layer includes a current sense resistor including a first current sense resistor metallic strip coupled between a first cross…

Techniques and circuitry for configuring and calibrating an integrated circuit

Granted: June 6, 2017
Patent Number: 9673824
A technique for configuring an integrated circuit includes receiving configuration data from an external element with an interface circuit. The configuration data may include an identification field and an instruction for configuring a logic block. Configuration circuitry may be used to identify the logic block to be configured based on the identification field. A storage element in the identified logic block is configured by the configuration circuitry based on the instruction.

Emulation of synchronous pipeline registers in integrated circuits with asynchronous interconnection resources

Granted: May 30, 2017
Patent Number: 9665670
Integrated circuits may include synchronous nodes and asynchronous routing elements coupled between the synchronous nodes. A synchronous design implemented in such an integrated circuit may identify a register chain having a source register, a destination register, and intermediate registers. A virtual register may be created for each of the intermediate registers, which may then be removed from the synchronous design. The created virtual registers may be connected in series to form a…

Low complexity cost function for sub-pixel motion estimation

Granted: May 30, 2017
Patent Number: 9667960
Methods and circuitry are provided for finding an optimum vector for motion-compensated prediction in video coding. Processing circuitry is operable to define a block in an image, the defined block having a plurality of pixels. A first set of residuals is calculated using a first motion vector. Each residual of the first set of residuals corresponds to a respective pixel within the plurality of pixels. Additionally, a first plurality of absolute differences is calculated. Each absolute…

Local constraints for motion matching

Granted: May 30, 2017
Patent Number: 9667991
A method and apparatus for estimating the motion of an image region (the “center” region) from a source video frame to a target video frame. The motion estimation is locally constrained in that the estimated motion of the “center region” is affected by the estimated motion of neighboring regions. Advantageously, this may reduce common motion matching problems such as false and ambiguous matches. In one embodiment, the locally-constrained motion estimation may be implemented by…