Altera Patent Grants

Specialized processing block with embedded pipelined accumulator circuitry

Granted: February 21, 2017
Patent Number: 9575725
A specialized processing block on an integrated circuit is provided that performs pipelined floating-point accumulation operations. The specialized processing block may be configured to perform one accumulation operation and produce the result of the accumulation at every other clock cycle. Alternatively, the specialized processing block may be configured to perform two independent accumulation operations and produce the result of each of the accumulation operations alternating at…

Integrated circuits with error handling capabilities

Granted: February 21, 2017
Patent Number: 9575862
A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals.…

Partial reconfiguration compatibility detection in an integrated circuit device

Granted: February 21, 2017
Patent Number: 9576095
Methods for partial reconfiguration compatibility detection in an integrated circuit device are disclosed. A disclosed method includes storing a unique identifier that identifies a partial reconfiguration region of the integrated circuit device in a storage circuit. A control circuit may receive an input partial reconfiguration data that activates the operations of the partial reconfiguration region. The method further includes comparing the input partial reconfiguration data to the…

Multiport memory element circuitry

Granted: February 21, 2017
Patent Number: 9576617
Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching…

Register initialization using multi-pass configuration

Granted: February 21, 2017
Patent Number: 9576625
A method includes clearing configuration bits of a plurality of latches of an integrated circuit. The method also includes implementing an initialization routing pattern of the plurality of latches by configuring the configuration bits of the plurality of latches. The method further includes storing initialization data in a set of the plurality of latches based on the initialization routing pattern. The method includes clearing the configurations bit of the plurality of latches, wherein…

Stability-enhanced physically unclonable function circuitry

Granted: February 21, 2017
Patent Number: 9577637
A Physically Unclonable Function circuit may include precharge circuitry that precharges an output. The precharge circuitry may include transistors of a first type such as N-type or P-type. Circuitry having only transistors of a second, different type may be coupled to the output. The circuitry may produce a signal at the output based on variations between the transistors of the second type. The circuitry may include first and second circuits such as first and second transistors of the…

Secure partial reconfiguration regions

Granted: February 21, 2017
Patent Number: 9577643
Systems and methods for partially reconfiguring a programmable IC device are presented. Processing circuitry on the programmable IC device may identify a first region of the IC device to be reconfigured from a received bitstream. The processing circuitry may read a configuration bit associated with the identified first region, and determine, based on the configuration bit, whether to permit the received bitstream to reconfigure the identified first region. The received bitstream may be…

Methods and apparatus for reducing power in clock distribution networks

Granted: February 21, 2017
Patent Number: 9577649
Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in…

Secure bitstream authentication

Granted: February 21, 2017
Patent Number: 9577822
Methods and systems are provided for securely authenticating data of an integrated circuit. By authenticating data having keystream blocks inserted between ciphertext portions, it becomes more difficult to mount successful authentication-based attacks.

Method and apparatus for performing fast incremental physical design optimization

Granted: February 14, 2017
Patent Number: 9569574
A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second,…

Reducing transactional latency in address decoding

Granted: February 14, 2017
Patent Number: 9570134
Techniques for reducing latency in address decoding are described. According to one approach, a method of operating an addressing circuit comprises partitioning range of encoded addresses into a first and second subset of encoded addresses, sending a first encoded address to a address decode circuit from a controller. In response to determining that the first encoded address is contained in the first subset, decoding the first encoded address in a first duration. In response to…

Via structure and method for its fabrication

Granted: February 14, 2017
Patent Number: 9570342
In a preferred embodiment of the invention, the via comprises one or more stacks, each stack comprising a seed layer of a first electrically conducting material formed on a smooth surface; a trace of a second electrically material that is electroplated on the seed layer; a column in electrical contact with the trace, the column comprising a third electrically conducting material that is electroplated on the trace; and an insulating material on the substrate and trace, the insulating…

Input voltage clamp with signal splitting and cross-over capabilities

Granted: February 14, 2017
Patent Number: 9571075
An integrated circuit with input voltage clamping circuitry for receiving an input signal from external devices is provided. The input voltage clamping circuitry may include a voltage splitting and clamping circuit, a selectively enabled transmission gate circuit, and a digitization and clamping circuit. The voltage splitting and clamping circuit may be configured to split the input signal into at least two separate components each of which is limited to a predetermined voltage swing.…

Methods and apparatus for reducing spatial overlap between routing wires

Granted: February 7, 2017
Patent Number: 9564394
An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may…

Circuits and methods for variable gain amplifiers

Granted: February 7, 2017
Patent Number: 9564863
A variable gain amplifier circuit includes a differential pair of transistors and a variable current source circuit. The differential pair of transistors generates an output signal based on an input signal. The variable current source circuit is coupled to the differential pair of transistors. A gain of the output signal relative to the input signal varies in response to variations in a bias current through the variable current source circuit. The variable gain amplifier circuit…

Non-intrusive monitoring and control of integrated circuits

Granted: January 31, 2017
Patent Number: 9558090
A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an…

Integrated circuit with bonding circuits for bonding memory controllers

Granted: January 31, 2017
Patent Number: 9558131
An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the…

Systems and methods for maintaining memory access coherency in embedded memory blocks

Granted: January 31, 2017
Patent Number: 9558796
Enhanced memory circuits are described that maintain coherency between concurrent memory reads and writes in a pipelined memory architecture. The described memory circuits can maintain data coherency regardless of the amount of pipelining applied to the memory inputs and/or outputs. Moreover, these memory circuits may be implemented as dedicated hard circuits in a field programmable gate array (FPGA) or other programmable logic device (PLD), and can be supplemented with user-configurable…

Multi-rate transceiver circuitry

Granted: January 31, 2017
Patent Number: 9559834
Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may…

Transceiver system with reduced latency uncertainty

Granted: January 31, 2017
Patent Number: 9559881
A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the…