Altera Patent Grants

Accelerator architecture on a programmable platform

Granted: October 24, 2023
Patent Number: 11797473
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

Network functions virtualization platforms with function chaining capabilities

Granted: June 27, 2023
Patent Number: 11687358
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine…

Flexible physical function and virtual function mapping

Granted: June 13, 2023
Patent Number: 11675613
Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

Multichip package with protocol-configurable data paths

Granted: June 6, 2023
Patent Number: 11669479
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…

Distributed multi-die protocol application interface

Granted: May 23, 2023
Patent Number: 11657016
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels.…

Joining patient EHR data with community patient data

Granted: April 25, 2023
Patent Number: 11636926
Providing healthcare services based on the combination of data from electronic healthcare records (EHRs) and community patient data includes: retrieving EHR data from an EHR database for a patient; retrieving community patient data for the patient; and providing clinical decision support for a healthcare provider at a computing device of the healthcare provider by interjecting, into a clinical workflow that utilizes the retrieved EHR data, the retrieved community patient data such that…

Systems and methods for data transfer over a shared interface

Granted: April 4, 2023
Patent Number: 11620250
A method for compressing is provided. The method includes compressing, via a processor, a portion of a first data packet to generate a second data packet having a compressed portion. The method includes transmitting the second data packet having the compressed portion via an interface to a co-processor. The processor and the co-processor are communicatively coupled via the interface. The method also includes unpacking, via the co-processor, the compressed portion of the second data…

Systems and methods for data transfer over a shared interface

Granted: April 4, 2023
Patent Number: 11620250
A method for compressing is provided. The method includes compressing, via a processor, a portion of a first data packet to generate a second data packet having a compressed portion. The method includes transmitting the second data packet having the compressed portion via an interface to a co-processor. The processor and the co-processor are communicatively coupled via the interface. The method also includes unpacking, via the co-processor, the compressed portion of the second data…

Graphical user interface methodologies for alerting a healthcare practitioner to newly displayed clinical information

Granted: February 7, 2023
Patent Number: 11574710
A method includes accessing, by a healthcare practitioner via an EHR software application loaded on an electronic device, patient information for a patient; determining, by an agent application loaded on the electronic device, the patient for which the patient information was accessed; communicating, from the agent application to an agent service, a request for data regarding the patient; communicating, from the agent service to the agent application, accessed community data for the…

Graphical user interface methodologies for providing specialty views of healthcare data

Granted: February 7, 2023
Patent Number: 11574711
A medical software application is configurable to allow different specialty views to be specified for healthcare practitioners having different characteristics (e.g. specialists in different fields), based on, for example, role or specialty information for a logged in user. A specialty view is further be configured to affect the display of data within a domain. A specialty view can specify that a certain vocabulary takes priority for display purposes (e.g. display ordering).

Network processor FPGA (npFPGA): multi-die-FPGA chip for scalable multi-gigabit network processing

Granted: December 6, 2022
Patent Number: 11520394
Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The…

Method and apparatus for performing incremental compilation using structural netlist comparison

Granted: November 22, 2022
Patent Number: 11507723
A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

Method and apparatus for performing incremental compilation using structural netlist comparison

Granted: November 22, 2022
Patent Number: 11507722
A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

Methods for optimizing circuit performance via configurable clock skews

Granted: October 25, 2022
Patent Number: 11480993
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and…

Systems and methods for detecting and mitigating programmable logic device tampering

Granted: September 6, 2022
Patent Number: 11436382
Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected.…

Programmable logic device virtualization

Granted: April 12, 2022
Patent Number: 11303279
A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the…

Multichip package with protocol-configurable data paths

Granted: April 5, 2022
Patent Number: 11294842
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…

Methods and apparatus for selectively extracting and loading register states

Granted: March 29, 2022
Patent Number: 11287870
Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit.…

Integrated circuit device with embedded programmable logic

Granted: March 22, 2022
Patent Number: 11281605
Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may…

Hybrid programmable many-core device with on-chip interconnect

Granted: February 22, 2022
Patent Number: 11256656
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The…