Altera Patent Grants

System and methods for adjusting memory command placement

Granted: August 15, 2017
Patent Number: 9733855
Integrated circuits may include memory interface circuitry operable to communicate with memory. The memory interface circuitry may include a memory controller and a memory interface circuit. The memory controller may fulfill memory access requests using the memory interface circuit. The memory controller may operate based on controller clock cycles of a controller clock, whereas the memory interface circuit may operate based on memory clock cycles of a memory clock. Each controller clock…

Apparatus and methods for on-die temperature sensing to improve FPGA performance

Granted: August 15, 2017
Patent Number: 9735779
A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.

Multi-function, multi-protocol FIFO for high-speed communication

Granted: August 15, 2017
Patent Number: 9736086
Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

Transceiver parameter solution space visualization to reduce bit error rate

Granted: August 8, 2017
Patent Number: 9727402
Techniques and mechanisms provide a solution space visualization of bit error rates (BER) for combinations of parameter settings of transceivers. Different types of visualizations may be generated.

Method and apparatus for secure provisioning of an integrated circuit device

Granted: August 8, 2017
Patent Number: 9729518
A method of operating an integrated circuit may include generating a session key with a random number generator circuit. The session key may then be used to establish a secure communications channel between the integrated circuit and a remote server. The integrated circuit may be placed in a non-operational mode prior to establishing the secure communications channel. Accordingly, in response to establishing the secure communications channel, the integrated circuit may be placed in an…

Method and system for calculating timing variations considering simultaneous switching noise

Granted: August 1, 2017
Patent Number: 9721047
A computer implemented method for determining a timing variation for an edge of a waveform under simultaneous switching noise (SSN) conditions is provided. The method includes characterizing an impact of mutual inductive relationships on a pin while the pin is at a quiet state and characterizing a signal edge applied to the pin. The signal edge can be characterized by the slew rate in one embodiment. A voltage change related to a curve characterizing the impact of mutual inductive…

Security variable scrambling

Granted: August 1, 2017
Patent Number: 9722778
Methods and systems are provided for securing an integrated circuit device against various security attacks, such as side-channel attacks. By limiting the number of different challenge vectors that can be combined with a critical variable of an encryption operation, it becomes more difficult to create enough side channel measurements to successfully perform statistical side-channel analysis.

Method and apparatus for performing register retiming in the presence of timing analysis exceptions

Granted: July 18, 2017
Patent Number: 9710591
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

On-die input reference voltage with self-calibrating duty cycle correction

Granted: July 18, 2017
Patent Number: 9711189
A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that…

Serial memory interface circuitry for programmable integrated circuits

Granted: July 18, 2017
Patent Number: 9712186
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet…

Self-stuffing multi-clock FIFO requiring no synchronizers

Granted: July 11, 2017
Patent Number: 9703526
An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers.…

Guided memory buffer allocation

Granted: July 11, 2017
Patent Number: 9703696
Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.

Secure physically unclonable function (PUF) error correction

Granted: July 11, 2017
Patent Number: 9703989
An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may be part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may differ from the desired PUF…

Power gated lookup table circuitry

Granted: July 11, 2017
Patent Number: 9705504
A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary…

Field programmable gate array with integrated application specific integrated circuit fabric

Granted: July 11, 2017
Patent Number: 9705506
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA…

Integrated circuit with continuously adaptive equalization circuitry

Granted: July 11, 2017
Patent Number: 9705708
An integrated circuit for supporting a high-speed communications link is provided. The integrated circuit may include equalization circuitry having a continuous time linear equalizer (CTLE) circuit, a decision feedback equalizer (DFE) circuit, and associated adaptation logic for controlling the CTLE circuit and the DFE circuit. The adaptation logic may include an error minimization adaptation circuit operable to generate at least a first post-cursor value, a signal amplitude detection…

Fixed-point and floating-point optimization

Granted: July 4, 2017
Patent Number: 9696991
Systems and methods for enhancing fixed-point operations, floating-point operations, or a combination thereof for programs implemented on an integrated circuit (IC) are provided. Portions of these operations may be shared among the operations. Accordingly, the embodiments described herein enhance these fixed-point operations, floating-point operations, or a combination thereof based upon these portions of the operations that may be shared.

Metastability-hardened synchronization circuit

Granted: July 4, 2017
Patent Number: 9697309
An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

State visibility and manipulation in integrated circuits

Granted: July 4, 2017
Patent Number: 9697318
In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an…

Apparatus for stacked electronic circuitry and associated methods

Granted: July 4, 2017
Patent Number: 9698123
An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.