Altera Patent Grants

Selectable reconfiguration for dynamically reconfigurable IP cores

Granted: April 25, 2017
Patent Number: 9633158
Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and…

Integrated circuit package with active interposer

Granted: April 25, 2017
Patent Number: 9633872
An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit…

Package substrate warpage reshaping apparatus and method

Granted: April 25, 2017
Patent Number: 9633874
A warpage reshaping apparatus to reshape a warpage profile of a package substrate is disclosed. The warpage reshaping apparatus includes a metal boat, a plurality of planar boards and a plurality of spring-loaded clips. The metal boat includes a plurality of cavities. Package substrates are placed into each of the cavities. Each of the plurality of planar boards is disposed on a respective one of the package substrates. The spring-loaded clips have a first portion coupled to the metal…

Strain-enhanced transistors with adjustable layouts

Granted: April 25, 2017
Patent Number: 9634094
A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial…

Method and apparatus for generating systolic arrays on a target device using a high-level synthesis language

Granted: April 18, 2017
Patent Number: 9626165
A method for generating a description of a systolic array includes prompting a user to input information about the systolic array. A high-level synthesis language is generated that describes channels of processing elements of the systolic array and a topology of the processing elements in response to the information provided by the user.

Repartitioning and reordering of multiple threads into subsets based on possible access conflict, for sequential access to groups of memory banks in a shared memory

Granted: April 18, 2017
Patent Number: 9626218
Circuitry for dynamically ordering the execution of multiple threads in parallel is presented. The circuitry may include a control circuit that controls the execution of multiple subsets of threads using multiple processing units in parallel. Each of the plurality of processing units may be associated with an adjustable order thread issuer that may receive a subset of threads and an order in which to execute the subset of threads from the control circuit. The adjustable order thread…

High speed FPGA boot-up through concurrent multi-frame configuration scheme

Granted: April 18, 2017
Patent Number: 9627019
Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address…

Apparatus and associated methods for capacitors with improved density and matching

Granted: April 18, 2017
Patent Number: 9627138
Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The…

Well-tap structures for analog matching transistor arrays

Granted: April 18, 2017
Patent Number: 9627529
In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures and multiple well-tap structures. The array of dummy structures surrounds the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. In one embodiment, each of the well-tap structures may include a well, a diffusion region and a gate-like structure. The well may be formed in a substrate and…

Parameterizable method for simulating PLL behavior

Granted: April 18, 2017
Patent Number: 9628095
Methods for designing and developing models for simulating the behavior of clock signals and in particular those generated by phase-locked loop (PLL) circuits are provided. The clock period of a phase-locked loop circuit's variable frequency oscillator signal may be modeled by combining the inverse of the oscillator frequency rounded up to the simulation time scale with the inverse rounded down to the simulation time scale. The variable frequency oscillator signal may further be…

Digital equalizer adaptation using on-die instrument

Granted: April 18, 2017
Patent Number: 9628304
Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry…

Pseudo-random bit sequence generator

Granted: April 11, 2017
Patent Number: 9619206
The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).

Circuitry and methods for implementing Galois-field reduction

Granted: April 11, 2017
Patent Number: 9619207
Galois-field reduction circuitry for reducing a Galois-field expansion value using an irreducible polynomial includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective expansion bit position. Gates select ones of said the plurality of memories corresponding to ones of the respective expansion bit positions that contain β€˜1’, and an exclusive-OR gate combines outputs of the gates that select. A specialized processing…

Memory-mapped state bus for integrated circuit

Granted: April 11, 2017
Patent Number: 9619423
Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the…

Control block size reduction through IP migration in an integrated circuit device

Granted: April 11, 2017
Patent Number: 9619610
Methods for control block size reduction of a controller of an integrated circuit (IC) device through intellectual property (IP) migration in the IC device are disclosed. A disclosed method includes receiving configuration data for the IC device and determining whether IP construction data is defined in the configuration data. The IP construction data contains instruction sets for implementing logical operations of a controller-based IP core in a core region of the IC device. Such data…

Iterative frame synchronization for multiple-lane transmission

Granted: April 11, 2017
Patent Number: 9621467
One embodiment relates to a data transmission circuit with deterministic flow control that includes a plurality of FIFO buffers, a plurality of transmitter lanes, a transmitter MAC circuit, and a transmitter aligner circuit. The transmitter aligner circuit includes control circuitry that performs one or more iterations of a procedure to optimize a starting offset, where the starting offset provides an initial delay between the writing of the data bits to the plurality of FIFO buffers and…

Digital signal processing blocks with embedded arithmetic circuits

Granted: April 4, 2017
Patent Number: 9613232
A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of…

Integrated circuit (IC) with primary and secondary networks and device containing such an IC

Granted: March 28, 2017
Patent Number: 9606176
Some embodiments provide an integrated circuit (β€œIC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary…

Configurable clock grid structures

Granted: March 28, 2017
Patent Number: 9606573
Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second…

Low power optimizations for a floating point multiplier

Granted: March 28, 2017
Patent Number: 9606608
Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device…