APPARATUSES AND SYSTEMS FOR OFFSET CROSS FIELD-EFFECT TRANSISTORS
Granted: May 2, 2024
Application Number:
20240145565
The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not…
VARIABLE BIT MORTON CODES
Granted: May 2, 2024
Application Number:
20240144581
A technique for performing ray tracing operations is provided. The technique includes determining a set of keys and a set of values corresponding to dimensions of a bounding box for a scene; sorting the set of keys and the set of values to generate a sorted set of values; and based on the sorted set of values, generating a Morton code for a triangle of the scene.
SPLIT-BASED TREES FOR RAY TRACING
Granted: May 2, 2024
Application Number:
20240144580
Devices and methods are provided for generating an accelerated data structure for ray tracing which include generating a first splitting plane at a first location of a space comprising objects represented by geometry, constructing a first level of an accelerated data structure based on portions of the geometry, straddling the first splitting plane, which are classified as located on opposing sides of the first splitting plane, after constructing the first level of the accelerated data…
Stability Testing for Memory Overclocking
Granted: May 2, 2024
Application Number:
20240143445
Stability testing for memory overclocking is described. In accordance with the described techniques, operation of a memory with overclocked memory settings is testing during a boot up process of a computing device. Test results based on the testing are exposed via a user interface. The test results predict a stability of the memory over a subsequent time period if the memory is configured to operate with the overclocked memory settings.
SOFTWARE COMPILATION FOR NETWORKED PROCESSING SYSTEM
Granted: May 2, 2024
Application Number:
20240143295
A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.
Sparse Matrix Operations Using Processing-in-Memory
Granted: May 2, 2024
Application Number:
20240143199
Sparse matrix operations using processing-in-memory is described. In accordance with the described techniques, a processing-in-memory component of a memory module receives a request for a vector element stored at a first location in memory of the memory module. The processing-in-memory component identifies an index value for a non-zero element in a sparse matrix using a representation of the sparse matrix stored at a second location in the memory. The processing-in-memory component then…
HYBRID RENDER WITH DEFERRED PRIMITIVE BATCH BINNING
Granted: April 25, 2024
Application Number:
20240135626
A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin…
Data Routing for Efficient Decompression of Compressed Data Stored in a Cache
Granted: April 25, 2024
Application Number:
20240134793
Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes…
READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES
Granted: April 11, 2024
Application Number:
20240119993
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only…
WIFI PACKET COALESCING
Granted: April 11, 2024
Application Number:
20240121192
The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register.…
INCREASING SYSTEM POWER EFFICIENCY BY OPTICAL COMPUTING
Granted: April 4, 2024
Application Number:
20240111355
Methods and systems are disclosed for reducing power consumption by a system including a digital unit and an optical unit. Techniques disclosed comprise generating a workload signature of an incoming workload to be executed by the system. Based on the generated workload signature, techniques disclosed comprise matching the incoming workload with a profile of stored workload profiles. The workload profiles are generated by a trace capture unit. Based on the associated profile, a task…
SIGNAL INTERFERENCE TESTING USING RELIABLE READ WRITE INTERFACE
Granted: April 4, 2024
Application Number:
20240112747
A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially…
DIRECTED REFRESH MANAGEMENT FOR DRAM
Granted: April 4, 2024
Application Number:
20240112722
A memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. In response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. In response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.
UNMATCHED CLOCK FOR COMMAND-ADDRESS AND DATA
Granted: April 4, 2024
Application Number:
20240112720
A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that…
MEMORY ACCESS ENGINE
Granted: April 4, 2024
Application Number:
20240111688
A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.
Runtime Flushing to Persistency in Heterogenous Systems
Granted: April 4, 2024
Application Number:
20240111682
Runtime flushing to persistency in heterogenous systems is described. In accordance with the described techniques, a system may include a persistent memory in electronic communication with at least one cache and a controller configured to command the at least one cache to flush dirty data to the persistent memory in response to a dirtiness of the at least one cache reaching a cache dirtiness threshold.
Selecting Between Basic and Global Persistent Flush Modes
Granted: April 4, 2024
Application Number:
20240111680
Selecting between basic and global persistent flush modes is described. In accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while…
Executing Kernel Workgroups Across Multiple Compute Unit Types
Granted: April 4, 2024
Application Number:
20240111591
Portions of programs, oftentimes referred to as kernels, are written by programmers to target a particular type of compute unit, such as a central processing unit (CPU) core or a graphics processing unit (GPU) core. When executing a kernel, the kernel is separated into multiple parts referred to as workgroups, and each workgroup is provided to a compute unit for execution. Usage of one type of compute unit is monitored and, in response to the one type of compute unit being idle, one or…
TAG AND DATA CONFIGURATION FOR FINE-GRAINED CACHE MEMORY
Granted: April 4, 2024
Application Number:
20240111425
A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored…
SPECULATIVE DRAM REQUEST ENABLING AND DISABLING
Granted: April 4, 2024
Application Number:
20240111420
Methods, devices, and systems for retrieving information based on cache miss prediction. It is predicted, based on a history of cache misses at a private cache, that a cache lookup for the information will miss a shared victim cache. A speculative memory request is enabled based on the prediction that the cache lookup for the information will miss the shared victim cache. The information is fetched based on the enabled speculative memory request.
