AMD Patent Grants

Phase locked loop system with bandwidth measurement and calibration

Granted: June 27, 2017
Patent Number: 9692426
A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the…

Low latency asynchronous interface circuits

Granted: June 20, 2017
Patent Number: 9685953
In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for…

Method and apparatus for aggregation and streaming of monitoring data

Granted: June 20, 2017
Patent Number: 9686536
A video device having data lanes and a method of operating the video device includes generating performance monitoring and/or debug data in response to the operation of the video device. The generated data is sampled from component of the video device operating in various clocking domain. The data sampled from the components is combined into a unified stream which is independent of the various clocking domain. The unified stream is transmitted across one more data lanes of a video link…

Method and apparatus for distributing processing core workloads among processing cores

Granted: June 13, 2017
Patent Number: 9678806
Briefly, methods and apparatus to rebalance workloads among processing cores utilizing a hybrid work donation and work stealing technique are disclosed that improve workload imbalances within processing devices such as, for example, GPUs. In one example, the methods and apparatus allow for workload distribution between a first processing core and a second processing core by providing queue elements from one or more workgroup queues associated with workgroups executing on the first…

Method and system for frame pacing

Granted: June 13, 2017
Patent Number: 9679345
A frame pacing method, computer program product, and computing system are provided for graphics processing. A method and system for frame pacing adds a delay which evenly spaces out the display of the subsequent frames, and a measurement mechanism which measures and adjusts the delay as application workload changes in an evenly spaced manner.

Flip-flop circuit with latch bypass

Granted: June 13, 2017
Patent Number: 9680450
In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The…

Hybrid system and method for determining performance levels based on thermal conditions within a processor

Granted: June 6, 2017
Patent Number: 9671767
A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature…

Configuring a cache management mechanism based on future accesses in a cache

Granted: June 6, 2017
Patent Number: 9672161
The described embodiments include a cache controller that configures a cache management mechanism. In the described embodiments, the cache controller is configured to monitor at least one structure associated with a cache to determine at least one cache block that may be accessed during a future access in the cache. Based on the determination of the at least one cache block that may be accessed during a future access in the cache, the cache controller configures the cache management…

Common mode extraction and tracking for data signaling

Granted: June 6, 2017
Patent Number: 9673849
Systems, apparatuses, and methods for performing common mode extraction for data communication are disclosed. A circuit is configured to receive a single-ended data signal on a first input port and couple the data signal to a positive input terminal of a receiver component. The circuit is also configured to receive a differential clock signal on second and third input ports and generate a reference signal from the differential clock signal. In one embodiment, the reference signal is…

Methods and apparatus for transcoding digital video

Granted: June 6, 2017
Patent Number: 9674523
Methods and apparatus for transcoding digital video data are disclosed. In an embodiment, a transcoder (300) decodes a digital video block (304) using a first coding scheme, such as 8×8 MPEG-2/4, to produce domain transformed data (306) and a motion vector (308). The transcoder (300) then estimates an energy level of each sub-block in the digital video block (304) in the frequency domain (as opposed to the spatial domain), thereby reducing or eliminating the need for motion…

Thermally-aware throttling in a three-dimensional processor stack

Granted: May 23, 2017
Patent Number: 9658663
A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of…

System and method for configuring boot-time parameters of nodes of a cloud computing system

Granted: May 23, 2017
Patent Number: 9658895
The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes…

Subcache affinity

Granted: May 23, 2017
Patent Number: 9658960
A method and apparatus for controlling affinity of subcaches is disclosed. When a core compute unit evicts a line of victim data, a prioritized search for space allocation on available subcaches is executed, in order of proximity between the subcache and the compute unit. The victim data may be injected into an adjacent subcache if space is available. Otherwise, a line may be evicted from the adjacent subcache to make room for the victim data or the victim data may be sent to the next…

Semiconductor device having a high-K gate dielectric above an STI region

Granted: May 23, 2017
Patent Number: 9659928
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench…

System and method for adjusting processor performance based on platform and ambient thermal conditions

Granted: May 16, 2017
Patent Number: 9652019
A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads…

Tracking source availability for instructions in a scheduler instruction queue

Granted: May 16, 2017
Patent Number: 9652305
A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the…

Moving data between caches in a heterogeneous processor system

Granted: May 16, 2017
Patent Number: 9652390
Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at…

Dynamic work partitioning on heterogeneous processing devices

Granted: May 9, 2017
Patent Number: 9645854
A method, system and article of manufacture for balancing a workload on heterogeneous processing devices. The method comprising accessing a memory storage of a processor of one type by a dequeuing entity associated with a processor of a different type, identifying a task from a plurality of tasks within the memory that can be processed by the processor of the different type, synchronizing a plurality of dequeuing entities capable of accessing the memory storage, and dequeuing the task…

Solution to divergent branches in a SIMD core using hardware pointers

Granted: May 2, 2017
Patent Number: 9639371
A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler generates code wherein when executed determines a size of a next very large instruction world (VLIW) to process and determine multiple pointer values to store in multiple corresponding PC registers in a target processor. The updated PC registers point to instructions intermingled from different…

Encoding valid data states in source synchronous bus interfaces using clock signal transitions

Granted: May 2, 2017
Patent Number: 9639488
Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or…