AMD Patent Grants

Technique for translating dependent instructions

Granted: August 15, 2017
Patent Number: 9733941
In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined source registers and a source register of the dependent operation. The new operation is independent of other pending operations and therefore can be executed without waiting for…

Methods and apparatus for data cache way prediction based on classification as stack data

Granted: August 15, 2017
Patent Number: 9734059
A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information…

Thin provisioning architecture for high seek-time devices

Granted: August 15, 2017
Patent Number: 9734081
A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin provisioning techniques can minimize disk seeks during command functions by utilizing a translation table and free list stored to both one or more physical storage devices as well as to a cache. The cached translation table and free list can be updated directly in response to disk write procedures. A read-only copy of the cached…

Memory page access detection

Granted: August 8, 2017
Patent Number: 9727241
A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.

Hybrid tag scheduler to broadcast scheduler entry tags for picked instructions

Granted: August 8, 2017
Patent Number: 9727340
The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also…

Method and system of sampling to automatically scale digital power estimates with frequency

Granted: August 8, 2017
Patent Number: 9727435
A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding…

Texel shading in texture space

Granted: August 8, 2017
Patent Number: 9728002
A graphics processing unit is configured to map pixels of a first frame of a video stream to texels, select a subset of the texels for shading based on previously cached texels that were shaded for a second frame, and shade the subset of the texels. The graphics processing unit is also configured to cache the shaded subset of the texels with the previously cached texels and determine values for the pixels of the first frame based on the cached texels.

Method and device for noise reduction in multi-frequency clocking environment

Granted: August 1, 2017
Patent Number: 9720486
A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain.…

Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration

Granted: August 1, 2017
Patent Number: 9720487
Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Data layout transformation for workload distribution

Granted: August 1, 2017
Patent Number: 9720708
Techniques are disclosed relating to data transformation for distributing workloads between processors or cores within a processor. In various embodiments, a first processing element receives a set of bytecode. The set of bytecode specifies a set of tasks and a first data structure that specifies data to be operated on during performance of the set of tasks. The first data structure is stored non-contiguously in memory of the computer system. In response to determining to offload the set…

Dependent instruction suppression

Granted: July 25, 2017
Patent Number: 9715389
A method includes suppressing execution of at least one dependent instruction of a load instruction by a processor using stored dependency information responsive to an invalid status of the load instruction. A processor includes an execution unit to execute instructions and a scheduler. The scheduler is to select for execution in the execution unit a load instruction having at least one dependent instruction and suppress execution of the at least one dependent instruction using stored…

Using temperature margin to balance performance with power allocation

Granted: July 18, 2017
Patent Number: 9710034
A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond…

Execution of instruction loops using an instruction buffer

Granted: July 18, 2017
Patent Number: 9710276
In a normal, non-loop mode a uOp buffer receives and stores for dispatch the uOps generated by a decode stage based on a received instruction sequence. In response to detecting a loop in the instruction sequence, the uOp buffer is placed into a loop mode whereby, after the uOps associated with the loop have been stored at the uOp buffer, storage of further uOps at the buffer is suspended. To execute the loop, the uOp buffer repeatedly dispatches the uOps associated with the loop's…

Virtual memory mapping for improved DRAM page locality

Granted: July 18, 2017
Patent Number: 9710392
Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by…

Using a cut mask to form spaces representing spacing violations in a semiconductor structure

Granted: July 18, 2017
Patent Number: 9710589
Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the…

Data transmission between asynchronous environments

Granted: July 18, 2017
Patent Number: 9712353
A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

Gate all around device architecture with local oxide

Granted: July 11, 2017
Patent Number: 9704995
A system and method for fabricating non-planar devices while managing short channel and heating effects are described. A semiconductor device fabrication process includes forming a non-planar device where the body of the device is insulated from the silicon substrate, but the source and drain regions are not insulated from the silicon substrate. The process builds a local silicon on insulator (SOI) while not insulating area around the source and drain regions from the silicon substrate.…

Direct hardware access media player

Granted: July 4, 2017
Patent Number: 9696784
A system, method and a computer program product for processing media content on a media player having direct access to hardware are provided in exemplary embodiments. When the media player is initialized, an operating system is placed into a stand-by mode that decreases power consumption on an electronic device. Instead of the operating system, a hardware pipeline processes media content. A hardware pipeline is dedicated to process a media content based on the media content type. The…

Power management through power gating portions of an idle processor

Granted: July 4, 2017
Patent Number: 9696790
Processor power may be managed by executing state storage and power gating instructions after receiving an idle indication. The idle indication may be received while the processor is executing instructions in a first mode, and the processor may execute the state storage and power gating instructions in a second mode. The state storage and power gating instructions may be inaccessible to the processor when operating in the first mode.

Programmable substitutions for microcode

Granted: July 4, 2017
Patent Number: 9696998
The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the…