AMD Patent Grants

Thermally-aware throttling in a three-dimensional processor stack

Granted: May 23, 2017
Patent Number: 9658663
A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of…

System and method for configuring boot-time parameters of nodes of a cloud computing system

Granted: May 23, 2017
Patent Number: 9658895
The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes…

Subcache affinity

Granted: May 23, 2017
Patent Number: 9658960
A method and apparatus for controlling affinity of subcaches is disclosed. When a core compute unit evicts a line of victim data, a prioritized search for space allocation on available subcaches is executed, in order of proximity between the subcache and the compute unit. The victim data may be injected into an adjacent subcache if space is available. Otherwise, a line may be evicted from the adjacent subcache to make room for the victim data or the victim data may be sent to the next…

Semiconductor device having a high-K gate dielectric above an STI region

Granted: May 23, 2017
Patent Number: 9659928
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench…

System and method for adjusting processor performance based on platform and ambient thermal conditions

Granted: May 16, 2017
Patent Number: 9652019
A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads…

Tracking source availability for instructions in a scheduler instruction queue

Granted: May 16, 2017
Patent Number: 9652305
A processor includes an execution unit to execute instructions and a scheduler unit to store a queue of instructions for execution by the execution unit. The scheduler unit includes a wake array including a plurality of source slots to store source identifiers for sources associated with the instructions, a picker to schedule a particular instruction for execution in the execution unit, broadcast a destination identifier associated with the particular instruction to a first subset of the…

Moving data between caches in a heterogeneous processor system

Granted: May 16, 2017
Patent Number: 9652390
Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at…

Dynamic work partitioning on heterogeneous processing devices

Granted: May 9, 2017
Patent Number: 9645854
A method, system and article of manufacture for balancing a workload on heterogeneous processing devices. The method comprising accessing a memory storage of a processor of one type by a dequeuing entity associated with a processor of a different type, identifying a task from a plurality of tasks within the memory that can be processed by the processor of the different type, synchronizing a plurality of dequeuing entities capable of accessing the memory storage, and dequeuing the task…

Power management of interactive workloads driven by direct and indirect user feedback

Granted: May 2, 2017
Patent Number: 9639140
A method of managing power state transitions for an interactive workload includes storing one or more parameters, each representing an electrical operating characteristic that controls power consumption of the processing unit, receiving a first user input requesting execution of a task by the processing unit, in response to receiving a second user input, modifying at least one of the one or more parameters, and executing the task in the processing unit while operating the processing unit…

Ordering memory commands in a computer system

Granted: May 2, 2017
Patent Number: 9639280
The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on the…

Thermal-aware compiler for parallel instruction execution in processors

Granted: May 2, 2017
Patent Number: 9639359
Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding…

Solution to divergent branches in a SIMD core using hardware pointers

Granted: May 2, 2017
Patent Number: 9639371
A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler generates code wherein when executed determines a size of a next very large instruction world (VLIW) to process and determine multiple pointer values to store in multiple corresponding PC registers in a target processor. The updated PC registers point to instructions intermingled from different…

Encoding valid data states in source synchronous bus interfaces using clock signal transitions

Granted: May 2, 2017
Patent Number: 9639488
Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or…

Integrated controller for training memory physical layer interface

Granted: May 2, 2017
Patent Number: 9639495
A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the…

Asynchronous submission of commands

Granted: April 25, 2017
Patent Number: 9632848
A system and method for allocating commands in processing is disclosed. The system and method includes an application running on a computer system that provides commands to be executed on one of a plurality of processors capable of executing the commands, the commands provided through an application programming interface, a device driver that buffers the streamed commands and converts the streamed commands into a format used by a GPU, and an operating system that builds a command buffer…

Integrated differential clock gater

Granted: April 18, 2017
Patent Number: 9625938
A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. The apparatus includes a latch circuit configured to…

Method and apparatus for floating point register caching

Granted: April 18, 2017
Patent Number: 9626190
The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also…

Data error correction device and methods thereof

Granted: April 18, 2017
Patent Number: 9626243
A method and device for error detection includes performing error detection for each data word received in a burst access to a memory. When no error is detected, the data words are written to a cache and indicated as valid data. In response to detecting an error in a data word, the error is corrected and the corrected data written to the cache without indicating the data as valid. In addition, the location of the detected error, indicating the data symbol associated with the error, is…

Apparatus and method for hash table access

Granted: April 18, 2017
Patent Number: 9626428
A system and method for accessing a hash table are provided. A hash table includes buckets where each bucket includes multiple chains. When a single instruction multiple data (SIMD) processor receives a group of threads configured to execute a key look-up instruction that accesses an element in the hash table, the threads executing on the SIMD processor identify a bucket that stores a key in the key look-up instruction. Once identified, the threads in the group traverse the multiple…

Implicit texture map parameterization for GPU rendering

Granted: April 18, 2017
Patent Number: 9626789
Embodiments are described for a method for processing textures for a mesh comprising quadrilateral polygons for real-time rendering of an object or model in a graphics processing unit (GPU), comprising associating an independent texture map with each face of the mesh to produce a plurality of face textures, packing the plurality of face textures into a single texture atlas, wherein the atlas is divided into a plurality of blocks based on a resolution of the face textures, adding a border…