AMD Patent Grants

Replica path timing adjustment and normalization for adaptive voltage and frequency scaling

Granted: February 21, 2017
Patent Number: 9575553
A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each…

Accelerated reversal of speculative state changes and resource recovery

Granted: February 21, 2017
Patent Number: 9575763
A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting…

Sidecar SRAM for high granularity in floor plan aspect ratio

Granted: February 21, 2017
Patent Number: 9575891
A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary…

Fine granularity refresh

Granted: February 21, 2017
Patent Number: 9576637
A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state…

Reducing power needed to send signals over wires

Granted: February 21, 2017
Patent Number: 9577618
Apparatus, computer readable medium, circuits, and method of reducing power in sending signals over two or more wires are disclosed. The method includes receiving two or more signals at a first end of the two or more wires. The method includes determining that the two or more signals should be encoded based at least on a previously received two or more signals. The method includes encoding the two or more signals. Additionally, the method includes sending the encoded two or more signals…

Method and apparatus for additive range reduction

Granted: February 7, 2017
Patent Number: 9563402
A method and apparatus for additive range reduction are disclosed. A constant may be pre-stored in a look-up table (LUT), and at least one section of the constant may be retrieved from the LUT for generating a product of an input argument and the constant such that a precision of the product may be controlled in any granularity. For a trigonometric function, 2/? is stored in the LUT, and at least one section of 2/? may be retrieved from the LUT. The argument is multiplied with the…

Precharge disable using predecoded address

Granted: February 7, 2017
Patent Number: 9563573
A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). A decoder adds the two address value to identify the read entry. Concurrently, a predecode module predecodes the two address values to identify a set of entries (e.g. two different entries) at the memory, whereby the set includes the entry to be read. The predecode module…

Floating point multiply accumulator multi-precision mantissa aligner

Granted: January 31, 2017
Patent Number: 9557963
A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and…

Minimizing latency from peripheral devices to compute engines

Granted: January 31, 2017
Patent Number: 9558133
Methods, systems, and computer program products are provided for minimizing latency in a implementation where a peripheral device is used as a capture device and a compute device such as a GPU processes the captured data in a computing environment. In embodiments, a peripheral device and GPU are tightly integrated and communicate at a hardware/firmware level. Peripheral device firmware can determine and store compute instructions specifically for the GPU, in a command queue. The compute…

Variable series resistance termination for wireline serial link transistor

Granted: January 31, 2017
Patent Number: 9558136
A variable series resistance termination circuit for wireline serial link transceivers is provided. Some embodiments include a pad for coupling to a wireline serial link and a termination circuit. The termination circuit includes a plurality of resistive components coupled in series with the pad and a plurality of switches. Each switch is to couple one or more of the plurality of resistive components in series between the pad and a termination voltage node when the switch is closed. A…

Mode-dependent access to embedded memory elements

Granted: January 24, 2017
Patent Number: 9552157
A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. When the first functional module is in the first mode, access to the embedded memory element is limited to the first functional module. At least one of the one or more other functional modules is provided with access…

Dynamically configuring regions of a main memory in a write-back mode or a write-through mode

Granted: January 24, 2017
Patent Number: 9552294
The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In…

Method and apparatus related to cache memory

Granted: January 24, 2017
Patent Number: 9552301
A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the…

Sampling circuit with reduced metastability exposure

Granted: January 24, 2017
Patent Number: 9552892
A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.

Dedicated interface for coupling flash memory and dynamic random access memory

Granted: January 17, 2017
Patent Number: 9547447
The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface…

Latency-aware memory control

Granted: January 3, 2017
Patent Number: 9535627
A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.

Page migration in a 3D stacked hybrid memory

Granted: January 3, 2017
Patent Number: 9535831
A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more…

IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect

Granted: January 3, 2017
Patent Number: 9535849
An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the…

Bimodal cooling in modular server system

Granted: January 3, 2017
Patent Number: 9538688
A server system includes a plurality of stacked modular computing structures. Each modular computing structure includes a circuit board comprising a computing resource, an air-fluid heat exchange structure comprising a first set of pipe segments, and a cold plate structure attached to a second set of pipe segments of the modular computing structure. The first set of pipe segments of each modular computing structure interfaces with the first set of pipe segments of at least one adjacent…

Asymmetric topology to boost low load efficiency in multi-phase switch-mode power conversion

Granted: December 27, 2016
Patent Number: RE46256
Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation.…