AMD Patent Grants

Scan flip-flop circuit with dedicated clocks

Granted: March 28, 2017
Patent Number: 9606177
In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data…

Dependence-based replay suppression

Granted: March 28, 2017
Patent Number: 9606806
A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a…

Generalized control registers

Granted: March 28, 2017
Patent Number: 9606936
Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from…

Scheduling of data migration

Granted: March 14, 2017
Patent Number: 9594521
In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Method and apparatus of adaptive application performance

Granted: March 14, 2017
Patent Number: 9594588
A method and apparatus of adaptive application performance includes a determination of at least one criteria for implementing adaptive application performance measures. Based upon the determination, adaptive application performance measures are implemented.

Media hardware resource allocation

Granted: March 14, 2017
Patent Number: 9594594
Apparatus, computer readable medium, and method of allocating media resources, the method including determining a media resources allocation table based on one or more media hardware resources and predetermined benchmarks of media hardware resources for performing media operations; in response to receiving a request for media resources from a first application, comparing the requested media resources with the media resources allocation table; and if the comparison indicates that the…

Efficient processor load balancing using predication flags

Granted: March 14, 2017
Patent Number: 9594595
A system and methods embodying some aspects of the present embodiments for efficient load balancing using predication flags are provided. The load balancing system includes a first processing unit, a second processing unit, and a shared queue. The first processing unit is in communication with a first queue. The second processing unit is in communication with a second queue. The first and second queues are each configured to hold a packet. The shared queue is configured to maintain a…

Voltage droop mitigation in 3D chip system

Granted: March 14, 2017
Patent Number: 9595508
The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one…

Flexible page sizes for virtual memory

Granted: March 7, 2017
Patent Number: 9588902
A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and…

Register file management for operations using a single physical register for both source and result

Granted: February 28, 2017
Patent Number: 9582286
A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute…

Remote task queuing by networked computing devices

Granted: February 28, 2017
Patent Number: 9582402
The described embodiments include a networking subsystem in a second computing device that is configured to receive a task message from a first computing device. Based on the task message, the networking subsystem updates an entry in a task queue with task information from the task message. A processing subsystem in the second computing device subsequently retrieves the task information from the task queue and performs the corresponding task. In these embodiments, the networking…

Replica path timing adjustment and normalization for adaptive voltage and frequency scaling

Granted: February 21, 2017
Patent Number: 9575553
A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each…

Accelerated reversal of speculative state changes and resource recovery

Granted: February 21, 2017
Patent Number: 9575763
A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting…

Sidecar SRAM for high granularity in floor plan aspect ratio

Granted: February 21, 2017
Patent Number: 9575891
A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary…

Fine granularity refresh

Granted: February 21, 2017
Patent Number: 9576637
A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state…

Reducing power needed to send signals over wires

Granted: February 21, 2017
Patent Number: 9577618
Apparatus, computer readable medium, circuits, and method of reducing power in sending signals over two or more wires are disclosed. The method includes receiving two or more signals at a first end of the two or more wires. The method includes determining that the two or more signals should be encoded based at least on a previously received two or more signals. The method includes encoding the two or more signals. Additionally, the method includes sending the encoded two or more signals…

Method and apparatus for additive range reduction

Granted: February 7, 2017
Patent Number: 9563402
A method and apparatus for additive range reduction are disclosed. A constant may be pre-stored in a look-up table (LUT), and at least one section of the constant may be retrieved from the LUT for generating a product of an input argument and the constant such that a precision of the product may be controlled in any granularity. For a trigonometric function, 2/? is stored in the LUT, and at least one section of 2/? may be retrieved from the LUT. The argument is multiplied with the…

Precharge disable using predecoded address

Granted: February 7, 2017
Patent Number: 9563573
A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). A decoder adds the two address value to identify the read entry. Concurrently, a predecode module predecodes the two address values to identify a set of entries (e.g. two different entries) at the memory, whereby the set includes the entry to be read. The predecode module…

Floating point multiply accumulator multi-precision mantissa aligner

Granted: January 31, 2017
Patent Number: 9557963
A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and…

Variable series resistance termination for wireline serial link transistor

Granted: January 31, 2017
Patent Number: 9558136
A variable series resistance termination circuit for wireline serial link transceivers is provided. Some embodiments include a pad for coupling to a wireline serial link and a termination circuit. The termination circuit includes a plurality of resistive components coupled in series with the pad and a plurality of switches. Each switch is to couple one or more of the plurality of resistive components in series between the pad and a termination voltage node when the switch is closed. A…