AMD Patent Grants

Dedicated interface for coupling flash memory and dynamic random access memory

Granted: January 17, 2017
Patent Number: 9547447
The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface…

Latency-aware memory control

Granted: January 3, 2017
Patent Number: 9535627
A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.

Page migration in a 3D stacked hybrid memory

Granted: January 3, 2017
Patent Number: 9535831
A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more…

IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect

Granted: January 3, 2017
Patent Number: 9535849
An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the…

Bimodal cooling in modular server system

Granted: January 3, 2017
Patent Number: 9538688
A server system includes a plurality of stacked modular computing structures. Each modular computing structure includes a circuit board comprising a computing resource, an air-fluid heat exchange structure comprising a first set of pipe segments, and a cold plate structure attached to a second set of pipe segments of the modular computing structure. The first set of pipe segments of each modular computing structure interfaces with the first set of pipe segments of at least one adjacent…

Asymmetric topology to boost low load efficiency in multi-phase switch-mode power conversion

Granted: December 27, 2016
Patent Number: RE46256
Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation.…

Interlocked increment memory allocation and access

Granted: December 27, 2016
Patent Number: 9529632
A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at least one pending write to the memory; and dynamically allocating respective contiguous blocks in the memory for each of the writer threads. Another method of allocating a memory to a plurality of concurrent threads includes launching the plurality of threads as a plurality of wavefronts, dynamically determining a group of wavefronts…

Batching modified blocks to the same dram page

Granted: December 27, 2016
Patent Number: 9529718
To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the…

Dynamic multithreaded cache allocation

Granted: December 27, 2016
Patent Number: 9529719
Apparatus and method embodiments for dynamically allocating cache space in a multi-threaded execution environment are disclosed. In some embodiments, a processor includes a cache shared by each of a plurality of processor cores and/or each of a plurality of threads executing on the processor. The processor further includes a cache allocation circuit configured to dynamically allocate space in the cache provided to each of the plurality of processor cores based on their respective usage…

Variable distance bypass between tag array and data array pipelines in a cache

Granted: December 27, 2016
Patent Number: 9529720
The present application describes embodiments of techniques for picking a data array lookup request for execution in a data array pipeline a variable number of cycles behind a corresponding tag array lookup request that is concurrently executing in a tag array pipeline. Some embodiments of a method for picking the data array lookup request include picking the data array lookup request for execution in a data array pipeline of a cache concurrently with execution of a tag array lookup…

Specialized memory disambiguation mechanisms for different memory read access types

Granted: December 20, 2016
Patent Number: 9524164
A system and method for efficient predicting and processing of memory access dependencies. A computing system includes control logic that marks a detected load instruction as a first type responsive to predicting the load instruction has high locality and is a candidate for store-to-load (STL) data forwarding. The control logic marks the detected load instruction as a second type responsive to predicting the load instruction has low locality and is not a candidate for STL data…

Generating flags for shifting and rotation operations in a processor

Granted: December 13, 2016
Patent Number: 9519483
A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured to generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A…

Priority-based command execution

Granted: December 13, 2016
Patent Number: 9519943
A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. Commands having the same priority are held in the same queue.

Decoupled selective implementation of entry and exit prediction for power gating processor components

Granted: November 29, 2016
Patent Number: 9507410
Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates…

Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta

Granted: November 29, 2016
Patent Number: 9507632
Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.

Coherency probe with link or domain indicator

Granted: November 29, 2016
Patent Number: 9507715
A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency…

Adjustment of write timing in a memory device

Granted: November 29, 2016
Patent Number: 9508408
A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted…

Memory cell supply voltage reduction prior to write cycle

Granted: November 29, 2016
Patent Number: 9508414
An integrated circuit device includes a memory cell coupled to a supply voltage line to receive a supply voltage and a voltage control circuit operable to reduce a magnitude of the supply voltage prior to a write cycle to the memory cell. The voltage control circuit includes a first capacitor that is selectively coupled between a supply voltage line and a first reference supply voltage line of the integrated circuit device in anticipation of a write cycle to the memory cell.

Automatic source code generation for accelerated function calls

Granted: November 22, 2016
Patent Number: 9501269
A programming model for a processor accelerator allows accelerated functions to be called from a main program directly without a management API for the accelerator. A compiler automatically generates wrapper source code for each accelerator function called by the application source code. The wrapper code is compiled, together with the accelerator source code, to generate an object file that is linked to an object file for the main program. By automatically generating the wrapper code, a…

Adaptive digital delay line for characterization of clock uncertainties

Granted: November 15, 2016
Patent Number: 9494649
An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay…