Split random number generator
Granted: March 5, 2024
Patent Number:
11924338
A computing system may implement a split random number generator that may use a random number generator to generate and store seed values in a memory for retrieval and use by one or more core processors to generate random numbers for secure processes within each core processor.
High to low level shifter architecture using lower voltage devices
Granted: March 5, 2024
Patent Number:
11923852
A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain…
Network command coalescing on GPUs
Granted: March 5, 2024
Patent Number:
11922207
An approach is provided for coalescing network commands in a GPU that implements a SIMT architecture. Compatible next network operations from different threads are coalesced into a single network command packet. This reduces the number of network command packets generated and issued by threads, thereby increasing efficiency, and improving throughput. The approach is applicable to any number of threads and any thread organization methodology, such as wavefronts, warps, etc.
Quantum circuit mapping for multi-programmed quantum computers
Granted: March 5, 2024
Patent Number:
11922107
Systems and methods are disclosed that map quantum circuits to physical qubits of a quantum computer. Techniques are disclosed to generate a graph that characterizes the physical qubits of the quantum computer and to compute the resource requirements of each circuit of the quantum circuits. For each circuit, the graph is searched for a subgraph that matches the resource requirements of the circuit, based on a density matrix. Physical qubits, defined by the matching subgraph, are then…
Flexible, scalable graph-processing accelerator
Granted: March 5, 2024
Patent Number:
11921784
An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host
Granted: March 5, 2024
Patent Number:
11921634
Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host is disclosed. In an implementation, a memory controller identifies a first write instruction to write first data to a first memory location, where the first write instruction is not a processing-in-memory (PIM) instruction. The memory controller then writes the first data to a first PIM register. Opportunistically, the memory controller moves the first data from the first PIM register to…
Single pass downsampler
Granted: February 27, 2024
Patent Number:
11915337
Systems, apparatuses, and methods for implementing a downsampler in a single compute shader pass are disclosed. A central processing unit (CPU) issues a single-pass compute shader kernel to perform downsampling of a texture on a graphics processing unit (GPU). The GPU includes a plurality of compute units for executing thread groups of the kernel. Each thread group fetches a patch of the texture, and each individual thread downsamples four quads of texels to compute mip levels 1 and 2…
Separating temperature domains in cooled systems
Granted: February 27, 2024
Patent Number:
11917794
Separating temperature domains in cooled systems, including: cooling at least one first component of a circuit board using a first cooling system; and conductively coupling the at least one first component to at least one second component using a superconductive portion of a power plane of the circuit board.
Method of operation for a data latch circuit
Granted: February 27, 2024
Patent Number:
11916556
The disclosed method of operation for a data latch (DLATCH) circuit may include receiving, by an input component of the DLATCH circuit, an input signal. The method may additionally include storing, by a combinatorial gate of the DLATCH circuit, a state of the input signal, wherein the combinatorial gate corresponds to at least one of an AND-OR-inverted (AOI22) cell or an OR-AND-inverted (OAI22) cell. The method may further include providing an output signal, by an output component of the…
Kernel software driven color remapping of rendered primary surfaces
Granted: February 27, 2024
Patent Number:
11915359
Systems, apparatuses, and methods for implementing kernel software driven color remapping of rendered primary surfaces are disclosed. A system includes at least a general processor, a graphics processor, and a memory. The general processor executes a user-mode application, a user-mode driver, and a kernel-mode driver. A primary surface is rendered on the graphics processor on behalf of the user-mode application. The primary surface is stored in memory locations allocated for the primary…
Method and apparatus for monitoring memory access traffic
Granted: February 27, 2024
Patent Number:
11914517
Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is…
Low temperature hybrid bonding
Granted: February 27, 2024
Patent Number:
11911839
A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first…
Delay-locked loop offset calibration and correction
Granted: February 20, 2024
Patent Number:
11909404
A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.
Stack-based ray traversal with dynamic multiple-node iterations
Granted: February 20, 2024
Patent Number:
11908065
A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
Processor with multiple op cache pipelines
Granted: February 20, 2024
Patent Number:
11907126
A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first…
Methods and apparatus for managing register free lists
Granted: February 20, 2024
Patent Number:
11907070
An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file.…
Memory allocation for processing-in-memory operations
Granted: February 13, 2024
Patent Number:
11900161
Memory allocation for processing-in-memory operations, including: receiving, by an allocation module, a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; determining a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern interleaves a plurality of component pages of a memory page across the plurality of data structure operands; and allocating the memory page based on…
Instant auto-focus with distance estimation
Granted: February 13, 2024
Patent Number:
11902658
Systems, apparatuses, and methods for implementing an instant auto-focus mechanism with distance estimation are disclosed. A camera includes at least an image sensor, one or more movement and/or orientation sensors, a timer, a lens, and control circuit. The control circuit receives first and second images captured by the image sensor of a given scene. The control circuit calculates a distance between first and second camera locations when the first and second images, respectively, were…
Region of interest (ROI)-based upscaling for video conferences
Granted: February 13, 2024
Patent Number:
11902571
Region of interest (ROI)-based upscaling for video conferences, the method including: identifying, in a video frame of a video conference at a first resolution, a boundary region for an object; applying, to a portion of the video frame bound by the boundary region, a machine learning upscaling algorithm to generate an upscaled portion of the video frame corresponding to a second resolution; and generating an upscaled video frame at the second resolution by combining a first plurality of…
Iterative indirect command buffers
Granted: February 13, 2024
Patent Number:
11900499
A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the…
