Method for adjusting an electronic system
Granted: December 9, 2008
Patent Number:
7463990
A method for adjusting an electronic system is provided in which it is possible to predefine the n parameters of the system which correspond to an n-dimensional adjustment space, wherein at the start of the adjustment each parameter has predefined for it two limit values that delimit an appropriate initial range in the n-dimensional adjustment space, and wherein the following steps are repeated until a termination condition is achieved: evaluating a target function that quantifies the…
Fluid sensor
Granted: December 2, 2008
Patent Number:
7458271
A fluid sensor is provided for determining a fluid characteristic, having an electronic sensor element that has an active surface for determining the fluid characteristic, having a mounting plate associated with the sensor element, and having a filter device associated with the sensor element for filtering the fluid, in which the active surface of the sensor element is oriented toward the mounting plate and in which the mounting plate is provided with an opening opposite from the active…
Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors
Granted: December 2, 2008
Patent Number:
7459368
Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconductor material, which is formed as a single crystal at least in the collector semiconductor region above the opening, is applied over the etch stop layer and over the opening. Before etching of the semiconductor material, a…
Array source line (AVSS) controlled high voltage regulation for programming flash or EE array
Granted: December 2, 2008
Patent Number:
7460411
A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS line to electrically float until the potential VAVSS is approximately equal to a reference potential Vref, and terminating the programming by de-coupling at least one of the current source and the potential source.
Apparatus and method for providing a temperature compensated reference current
Granted: November 25, 2008
Patent Number:
7456678
An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.
Method for preventing over-erasing of unused column redundant memory cells in a flash memory having single-transistor memory cells
Granted: November 25, 2008
Patent Number:
7457167
A method is provided for testing and for preventing over-erasure of unused redundant memory cells that can be subsequently used to replace defective memory cells in a Flash memory. An unused redundant memory cell is preprogrammed and tested simultaneously with each group of n memory cells. The selected unused redundant memory cell is preprogrammed only a couple of times and then skipped for the rest of the preprogramming pulses applied to the regular core cells. Each unused redundant…
Method of increasing reliability of packaged semiconductor integrated circuit dice
Granted: November 18, 2008
Patent Number:
7452733
Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in proximity to the failed dice frequently fail prematurely in the field. Therefore, in one embodiment, a method to identify those dice having a probability for early failure includes identifying a core die and a die cluster, adding the core die and at least one additional die from the die cluster to a…
Apparatus for eliminating leakage current of a low Vt device in a column latch
Granted: November 18, 2008
Patent Number:
7453725
An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A.…
Method and apparatus for a dual power supply to embedded non-volatile memory
Granted: November 11, 2008
Patent Number:
7450429
A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control circuit is configured to receive the external voltage level and the high voltage level, and to select one of the voltage levels. A memory array, with a word line and a bit line, is configured to receive the external and high voltage levels at the word line and the high voltage levels at the bit line.…
Accessing sequential data in microcontrollers
Granted: November 11, 2008
Patent Number:
7451367
A system and method for executing a sequential data memory access through a serial access port is provided. The system may include a memory access controller to receive a block access command and successively access data elements in the block. In certain implementations, a test device, such as a JTAG host, transmits a block read or write command specifying a start address and an increment value to an embedded device under test, whereupon a memory access controller in the embedded device…
Low voltage charge pump
Granted: November 4, 2008
Patent Number:
7446596
A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second…
Low voltage column decoder sharing a memory array p-well
Granted: November 4, 2008
Patent Number:
7447071
A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias…
Apparatus and method for implementing an analog-to-digital converter in programmable logic devices
Granted: November 4, 2008
Patent Number:
7446690
An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.
Low-power oscillator
Granted: October 28, 2008
Patent Number:
7443260
A circuit can include an oscillator core that outputs, in response to a bias signal, a periodic signal having an oscillation frequency; a bias circuit that, when powered, provides the bias signal (e.g., a voltage) to the oscillator core; and a switching circuit that periodically powers the bias circuit at a second frequency and provides the bias signal to the oscillator core when the bias circuit is not powered. The switching circuit can include a storage element that stores energy when…
Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement
Granted: October 21, 2008
Patent Number:
7439558
A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base region. The bipolar transistor may also include at least one other predetermined portion. The method and system also include providing at least one predetermined amount of oxygen to at least one of the compound base region, the…
Contactless nonvolatile memory array
Granted: October 21, 2008
Patent Number:
7439567
An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the…
System and method for controlling modulation
Granted: October 21, 2008
Patent Number:
7440515
A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.
Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation
Granted: October 14, 2008
Patent Number:
7435661
A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance…
Regenerative clock repeater
Granted: October 14, 2008
Patent Number:
7436232
A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high…
Circuit arrangement and method for increasing the functional range of a transponder
Granted: October 14, 2008
Patent Number:
7436286
A transponder receives its operating energy from an external source such as a radio signal or a battery. Such transponders are used for example in a vehicle or in a remote sensor. The response range of the transponder is increased by converting the received energy into an operating voltage which in turn is used to generate a function voltage required for performing a current function sequence. The generated function voltage is checked to determine at least one characteristic of the…
