Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns
Granted: February 6, 2024
Patent Number:
11892501
An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result…
Systems and methods for packing of transaction layer (TL) packets
Granted: January 30, 2024
Patent Number:
11886372
The present disclosure relates to packing transaction layer (TL) packets at a link layer of a protocol stack. In some examples, channel type data identify a type of message channel for a first TL packet can be generated. A set of slot formats for a slot for packing the first TL packet can be identified based on the channel type data and a slot format database. A respective slot format of the set of slot formats can be selected for the slot based on a message type of the first TL packet,…
Pattern detection based parameter adaptation
Granted: January 23, 2024
Patent Number:
11881883
An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter…
Multi-stage equalizer for inter-symbol interference cancellation
Granted: January 16, 2024
Patent Number:
11876650
An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given…
Dynamically updated delay line
Granted: January 16, 2024
Patent Number:
11876521
The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based…
Transmitter architecture for high speed memory interfaces
Granted: January 16, 2024
Patent Number:
11874788
Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel…
Method and system for optimizing a verification test regression
Granted: January 9, 2024
Patent Number:
11868241
A method for optimizing a verification regression includes obtaining data, by a processor, of previously executed runs of at least one verification regression session; extracting from the data, by the processor, values of one or a plurality of control knobs and values of one or a plurality verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression; finding, by the processor, correlation between said…
Systems and methods for distributed and parallelized emulation processor configuration
Granted: January 9, 2024
Patent Number:
11868786
Implementations may include a method of accelerated modification of an emulation processor system, by loading, by a first emulation processor, a first portion of processor instructions into one or more registers of the first emulation processor, in response to a selection of a first programming mode associated with the first emulation processor, and loading, by a second emulation processor operatively coupled with the first emulation processor, a second portion of the processor…
Context-aware circuit design layout construct
Granted: January 9, 2024
Patent Number:
11868698
Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the…
Driver resizing using a transition-based pin capacitance increase margin
Granted: January 9, 2024
Patent Number:
11868695
Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell…
Quantizing trained neural networks with removal of normalization
Granted: January 2, 2024
Patent Number:
11861492
Various embodiments provide for quantizing a trained neural network with removal of normalization with respect to at least one layer of the quantized neural network, such as a quantized multiple fan-in layer (e.g., element-wise add or sum layer).
Quantized softmax layer for neural networks
Granted: January 2, 2024
Patent Number:
11861452
Quantized softmax layers in neural networks are described. Some embodiments involve receiving, at an input to a softmax layer of a neural network from an intermediate layer of the neural network, a non-normalized output comprising a plurality of intermediate network decision values. Then for each intermediate network decision value of the plurality of intermediate network decision values, the embodiment involves: calculating a difference between the intermediate network decision value…
System and method for routing in an electronic design
Granted: January 2, 2024
Patent Number:
11861277
Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include enabling data transmission between plurality of protocol adapters, each of the protocol adapters including one ingress port and one egress port, wherein the ingress port of each of the plurality of protocol adapters maintains an active connection with a single egress port at one time. Embodiments may further include transmitting data between the plurality of protocol adapters…
Method, product, and system for dynamic design switching for high performance mixed signal simulation
Granted: December 19, 2023
Patent Number:
11847392
An approach is disclosed herein for dynamic design switching for high performance mixed signal simulation. Disclosed herein is a new approach to simulation processes that allows for different segments of a design to be swapped out without requiring re-elaboration. This is an improvement over current techniques and decreases the amount of time need to simulate a design. In some embodiments, the technique illustrated herein is combined with an automated triggering mechanism that controls…
Model-based simulation result predictor for circuit design
Granted: December 12, 2023
Patent Number:
11842130
Various embodiments provide for predicting a simulation result for a circuit design using a machine learning model, which can be used as part of a process of an electronic design automation (EDA) system that measures a circuit design (e.g., timing, power, voltage, current, etc.). In particular, various embodiments described herein can enable modeling simulated time measurements of a circuit design, and can enable such modeling with minimal usage of simulation result data.
Serializing and deserializing stage testing
Granted: November 28, 2023
Patent Number:
11829241
A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any…
Methods and circuits for reducing clock jitter
Granted: November 28, 2023
Patent Number:
11831323
A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.
High-bandwidth signal driver/receiver
Granted: November 28, 2023
Patent Number:
11831153
A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (?) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series…
System, method, and computer program product for predicting pin placement in an electronic design
Granted: November 28, 2023
Patent Number:
11829852
The present disclosure relates to a computer-implemented method for automatically determining pin placement associated with an electronic design. Embodiments may include receiving, using at least one processor, at least one layout associated with the electronic design and separating the at least one layout into one or more grids. Embodiments may also include extracting one or more connectivity features from the one or more grids, wherein the one or more connectivity features include…
System and method for monitoring compliance patterns
Granted: November 28, 2023
Patent Number:
11829276
Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to…
