Cavium Profile

Cavium Patent Grants

Memory interface with integrated tester

Patent Number 9568542 - February 14, 2017

In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a…

Distributed timer subsystem across multiple devices

Patent Number 9568944 - February 14, 2017

Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which…

Programmable ordering and prefetch

Patent Number 9569362 - February 14, 2017

An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a…

System and method to provide non-coherent access to a coherent memory system

Patent Number 9569366 - February 14, 2017

In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache…

Managing skew in data signals

Patent Number 9570128 - February 14, 2017

An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a…

Cavium Patent Applications

METHOD AND APPARATUS FOR HANDLING MODIFIED CONSTELLATION MAPPING USING A SOFT DEMAPPER

Application Number 20160294434 - October 6, 2016

A transceiver processing hardware (“TPH”) configured to processing wireless bit stream(s) includes a minimum mean square error…

METHOD AND APPARATUS FOR DISCARDING UNUSED POINTS FROM CONSTELLATION MAPPING RULE USING TRANSCEIVER PROCESSING HARDWARE ("TPH")

Application Number 20160294600 - October 6, 2016

An aspect of present invention discloses a transceiver processing hardware (“TPH”) which is configured to process wireless information…

HIGH PERFORMANCE SHIFTER CIRCUIT

Application Number 20160139879 - May 19, 2016

An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are…

METHOD TO MEASURE EDGE-RATE TIMING PENALTY OF DIGITAL INTEGRATED CIRCUITS

Application Number 20160140272 - May 19, 2016

Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models…

METHOD AND SYSTEM FOR IMPROVED LOAD BALANCING OF RECEIVED NETWORK TRAFFIC

Application Number 20160142320 - May 19, 2016

A method and a system embodying the method for load balancing of a received a packet based network traffic, comprising: receiving a packet at…

Cavium Federal Litigation Filings

Adaptive Data LLC v. Cavium Inc.

Delaware District Court - December 31, 2014

Open Network Solutions Inc. v. Cavium Inc.

Delaware District Court - May 21, 2014

FastVDO LLC v. Cavium Inc.

Delaware District Court - November 9, 2012

Harthcock v. MIPS Technologies Inc et al

Texas Eastern District Court - November 27, 2007