Cavium Patent Applications

METHOD AND APPARATUS FOR PROVIDING A LOW LATENCY TRANSMISSION SYSTEM USING ADAPTIVE BUFFERING ESTIMATION

Granted: March 2, 2017
Application Number: 20170063692
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example,…

Method and Apparatus for Providing a Low Latency Transmission System Using Adjustable Buffers

Granted: March 2, 2017
Application Number: 20170063959
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example,…

METHOD AND APPARATUS FOR HANDLING MODIFIED CONSTELLATION MAPPING USING A SOFT DEMAPPER

Granted: October 6, 2016
Application Number: 20160294434
A transceiver processing hardware (“TPH”) configured to processing wireless bit stream(s) includes a minimum mean square error (“MMSE”), an inverse discrete Fourier transform (“IDFT”), a demapper, a descrambler, and a combiner. While MMSE estimates transmit bit stream, IDFT generates samples associated with the frequency of bit stream. The demapper, in one embodiment, is configured to discard one or more unused constellation points relating to the frequency of bit stream from…

METHOD AND APPARATUS FOR DISCARDING UNUSED POINTS FROM CONSTELLATION MAPPING RULE USING TRANSCEIVER PROCESSING HARDWARE ("TPH")

Granted: October 6, 2016
Application Number: 20160294600
An aspect of present invention discloses a transceiver processing hardware (“TPH”) which is configured to process wireless information based on a constellation map. The TPH includes a minimum mean square error (“MMSE”), an inverse discrete Fourier transform (“IDFT”), and a demapper. The MMSE provides estimation of received bit stream, and the IDFT generates a list of samples associated with frequency of the bit stream. The demapper configured to discard unused constellation…

HIGH PERFORMANCE SHIFTER CIRCUIT

Granted: May 19, 2016
Application Number: 20160139879
An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter.

METHOD TO MEASURE EDGE-RATE TIMING PENALTY OF DIGITAL INTEGRATED CIRCUITS

Granted: May 19, 2016
Application Number: 20160140272
Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing…

METHOD AND SYSTEM FOR IMPROVED LOAD BALANCING OF RECEIVED NETWORK TRAFFIC

Granted: May 19, 2016
Application Number: 20160142320
A method and a system embodying the method for load balancing of a received a packet based network traffic, comprising: receiving a packet at a software defined network switch; determining information pertaining to uniqueness of a packet flow for the received packet; providing the determined information and the received packet to a network interface controller; and processing the received packet at the network interface controller in accordance with the provided determined information,…

APPARATUS AND METHOD FOR A MULTI-ENTITY SECURE SOFTWARE TRANSFER

Granted: May 19, 2016
Application Number: 20160142386
A method and a system embodying the method for a multi-entity secure software transfer, comprising, configuring a communication interface controller at each trusted hardware entity of a first hardware entity and a second hardware entity to disallow all external access except a communication link configuration access; establishing the communication link between the first hardware entity and the second hardware entity; configuring write access from the second hardware entity to only a…

NETWORK SWITCHING WITH CO-RESIDENT DATA-PLANE AND NETWORK INTERFACE CONTROLLERS

Granted: May 19, 2016
Application Number: 20160142520
A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal…

Method and Apparatus for Improving Data Integrity Using Compressed Soft Information

Granted: March 24, 2016
Application Number: 20160085615
A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. The process, in one aspect, is able to receive a data stream formatted with soft information from a communication network such as a wireless network. After identifying a set of bits representing a first logic value from a portion of the data stream in accordance with a predefined soft encoding scheme, the set of bits is compressed into a compressed set of bits. The…

Method and Apparatus for Quantizing Soft Information Using Non-Linear LLR Quantization

Granted: March 24, 2016
Application Number: 20160087757
A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. Upon receiving a set of signals representing a logic value from a transmitter via a physical communication channel, the set of signals is demodulated in accordance with a soft decoding scheme and subsequently, a Log Likelihood Ratio (“LLR”) value representing the logic value is generated. After generating a quantized LLR value in response to the LLR value via a…

Method and Apparatus for Quantizing Soft Information Using Linear Quantization

Granted: March 24, 2016
Application Number: 20160087758
A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. The process, in one aspect, is able to receive a data stream formatted with soft information from a communication network such as a wireless network. After identifying a set of bits representing a first logic value from a portion of the data stream in accordance with a predefined soft encoding scheme, the set of bits is compressed into a compressed set of bits. The…

METHOD AND AN APPARATUS FOR CO-PROCESSOR DATA PLANE VIRTUALIZATION

Granted: February 4, 2016
Application Number: 20160034288
A method and a system embodying the method for a data plane virtualization, comprising assigning each of at least one data plane a unique identifier; providing a request comprising an identifier of one of the at least one data plane together with an identifier of a virtual resource assigned to a guest; determining validity of the provided request in accordance with the identifier of the one of the at least one data plane and the identifier of the virtual resource assigned to the guest;…

SYSTEMS AND METHODS FOR NVME CONTROLLER VIRTUALIZATION TO SUPPORT MULTIPLE VIRTUAL MACHINES RUNNING ON A HOST

Granted: November 5, 2015
Application Number: 20150317088
A new approach is proposed that contemplates systems and methods to virtualize a physical NVMe controller associated with a computing device or host so that every virtual machine running on the host can have its own dedicated virtual NVMe controller. First, a plurality of virtual NVMe controllers are created on a single physical NVMe controller, which is associated with one or more storage devices. Once created, the plurality of virtual NVMe controllers are provided to VMs running on the…

SYSTEMS AND METHODS FOR AUTOMATED FUNCTIONAL COVERAGE GENERATION AND MANAGEMENT FOR IC DESIGN PROTOCOLS

Granted: October 22, 2015
Application Number: 20150302133
A new approach is proposed that contemplates systems and methods to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited…

Processing Of Finite Automata Based On Memory Hierarchy

Granted: October 15, 2015
Application Number: 20150293846
At least one processor may be operatively coupled to a plurality of memories and a node cache and configured to walk nodes of a per-pattern non-deterministic finite automaton (NFA). Nodes of the per-pattern NFA may be stored amongst one or more of the plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run…

Compilation of Finite Automata Based on Memory Hierarchy

Granted: October 15, 2015
Application Number: 20150295889
At least one per-pattern non-deterministic finite automaton (NFA) may be generated for a single regular expression pattern and may include a respective set of nodes. Nodes of the respective set of nodes of each per-pattern NFA generated may be distributed for storing in a plurality of memories based on hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run time performance for matching…

Processing of Finite Automata Based on a Node Cache

Granted: October 15, 2015
Application Number: 20150295891
Nodes of a per-pattern NFA may be stored amongst one or more of a plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels. At least one processor may be configured to cache one or more nodes of the per-pattern NFA in the node cache based on a cache miss of a given node of the one or more nodes and a hierarchical node…

METHOD AND APPARATUS FOR LOW LATENCY EXCHANGE OF DATA BETWEEN A PROCESSOR AND COPROCESSOR

Granted: September 17, 2015
Application Number: 20150261535
According to at least one example embodiment, a method of processing a wide command includes storing wide command data in a first physical structure of a processor. Information associated with the wide command is determined based on the wide command data and/or a corresponding memory address range associated with the wide command. The information associated with the wide command determined includes a size of the wide command and is stored in a second physical structure of the processor.…

Method and Apparatus for Memory Allocation in a Multi-Node System

Granted: September 10, 2015
Application Number: 20150253997
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the…