Cypress Semiconductor Patent Applications

Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions

Granted: August 3, 2017
Application Number: 20170221768
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly…

Quasi-differential Mutual Capacitance Measurement

Granted: July 20, 2017
Application Number: 20170205453
A circuit, system, and method for converting mutual capacitance to a digital value is described. Charge packets are transferred from a mutual capacitance to a pair of integration capacitors during alternate charge and discharge cycles. The time required to bring the discharged integration capacitor to the same potential as the charged integration capacitor with a current source is measured as a single-slope analog-to-digital converter (ADC). The output of the ADC is representative of the…

Configurable Capacitor Arrays and Switched Capacitor Circuits

Granted: July 13, 2017
Application Number: 20170201266
Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.

Split Gate Charge Trapping Memory Cells Having Different Select Gate and Memory Gate Heights

Granted: July 6, 2017
Application Number: 20170194343
A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.

MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE

Granted: June 29, 2017
Application Number: 20170186883
Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including…

Capacitive Fingerprint Sensor with Quadrature Demodulator and Multiphase Scanning

Granted: June 22, 2017
Application Number: 20170177920
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…

MEMORY INTERFACE CONFIGURABLE FOR ASYNCHRONOUS AND SYNCHRONOUS OPERATION AND FOR ACCESSING STORAGE FROM ANY CLOCK

Granted: June 15, 2017
Application Number: 20170165730
An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

ASYMMETRIC PASS FIELD-EFFECT TRANSISTOR FOR NONVOLATILE MEMORY

Granted: June 15, 2017
Application Number: 20170169888
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a…

GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE

Granted: June 15, 2017
Application Number: 20170170187
A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors…

METHOD FOR FABRICATING FERROELECTRIC RANDOM-ACCESS MEMORY ON PRE-PATTERNED BOTTOM ELECTRODE AND OXIDATION BARRIER

Granted: June 8, 2017
Application Number: 20170162249
Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric…

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

Granted: June 8, 2017
Application Number: 20170162586
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may…

Fingerprint Sensor-Compatible Overlay Material

Granted: May 18, 2017
Application Number: 20170140196
A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint…

METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE

Granted: March 30, 2017
Application Number: 20170090781
Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture.…

SYSTEMS, METHODS, AND DEVICES FOR PARALLEL READ AND WRITE OPERATIONS

Granted: March 16, 2017
Application Number: 20170076766
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to…

TAPE CHIP ON LEAD USING PASTE DIE ATTACH MATERIAL

Granted: February 16, 2017
Application Number: 20170047272
According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a…

SYSTEMS, METHODS, AND DEVICES FOR ENERGY AND POWER METERING

Granted: November 17, 2016
Application Number: 20160334445
Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated…

SYSTEMS, METHODS, AND DEVICES FOR TOUCH EVENT AND HOVER EVENT DETECTION

Granted: June 2, 2016
Application Number: 20160154507
Disclosed herein are systems, methods, and devices for touch event and hover event detection. Devices as disclosed herein may include a first electrode implemented in a capacitive sensor. The devices may also include a second electrode implemented in the capacitive sensor. The devices may further include a controller coupled to the first electrode and the second electrode, where the controller is configured to determine whether a touch event or a hover event has occurred based on a first…

LOW POWER CAPACITIVE SENSOR BUTTON

Granted: April 28, 2016
Application Number: 20160118980
Disclosed herein are system, methods, and apparatus for low power capacitive sensors. Apparatus may include a timing block configured to generate a repetitive trigger signal having a first frequency, and further configured to generate a clock signal having a second frequency. Apparatus may also include a sensing block coupled with the timing block and configured to, in response to the repetitive trigger signal, detect a change in capacitance associated with an object proximate to a…

CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED METHODS

Granted: April 21, 2016
Application Number: 20160111292
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor…

FORCE SENSOR BASELINE CALIBRATION

Granted: March 24, 2016
Application Number: 20160085355
Systems, methods, and apparatus for force sensor baseline calibration are disclosed herein. 1. Apparatus may include a force sensor configured to receive a plurality of force signals from a plurality of force sensitive elements, where the plurality of force signals is associated with a first touch at a first location of a sensing surface. The apparatus may include a touch sensor configured to receive a touch signal associated with the first touch. The apparatus may include processing…