Cypress Semiconductor Patent Applications

SYSTEMS, METHODS, AND DEVICES FOR ENERGY AND POWER METERING

Granted: November 17, 2016
Application Number: 20160334445
Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated…

SYSTEMS, METHODS, AND DEVICES FOR TOUCH EVENT AND HOVER EVENT DETECTION

Granted: June 2, 2016
Application Number: 20160154507
Disclosed herein are systems, methods, and devices for touch event and hover event detection. Devices as disclosed herein may include a first electrode implemented in a capacitive sensor. The devices may also include a second electrode implemented in the capacitive sensor. The devices may further include a controller coupled to the first electrode and the second electrode, where the controller is configured to determine whether a touch event or a hover event has occurred based on a first…

LOW POWER CAPACITIVE SENSOR BUTTON

Granted: April 28, 2016
Application Number: 20160118980
Disclosed herein are system, methods, and apparatus for low power capacitive sensors. Apparatus may include a timing block configured to generate a repetitive trigger signal having a first frequency, and further configured to generate a clock signal having a second frequency. Apparatus may also include a sensing block coupled with the timing block and configured to, in response to the repetitive trigger signal, detect a change in capacitance associated with an object proximate to a…

CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED METHODS

Granted: April 21, 2016
Application Number: 20160111292
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor…

FORCE SENSOR BASELINE CALIBRATION

Granted: March 24, 2016
Application Number: 20160085355
Systems, methods, and apparatus for force sensor baseline calibration are disclosed herein. 1. Apparatus may include a force sensor configured to receive a plurality of force signals from a plurality of force sensitive elements, where the plurality of force signals is associated with a first touch at a first location of a sensing surface. The apparatus may include a touch sensor configured to receive a touch signal associated with the first touch. The apparatus may include processing…

SYSTEMS, METHODS, AND DEVICES FOR BOOTSTRAPPED POWER CIRCUITS

Granted: March 3, 2016
Application Number: 20160062379
Systems, methods, and devices are disclosed for implementing a bootstrapped power circuit. Devices may include a controller configured to generate an output signal. Devices may include a power converter configured to receive the output signal, configured to store an amount of energy in response to receiving the output signal, and further configured to release the amount of energy in response to detecting a change in the output signal. Devices may include a switch configured to be toggled…

CAPACITANCE SENSING CIRCUITS AND METHODS

Granted: January 7, 2016
Application Number: 20160003881
A capacitance sense system can include a capacitance sense input configured to receive an input signal that varies according to a sensed capacitance; an integrator/discharge circuit configured to integrate the input signal and discharge the integrated input signal toward the reference level in conversion operations; and a remainder retainer section configured to quantize the discharging of the integrated input signal, and retain any remainder of the integrated input signal that follows a…

Single Layer Sensor Pattern

Granted: January 7, 2016
Application Number: 20160004343
An embodiment of a capacitive sensor array may comprise a first set of sensor electrodes each comprising one or more large subelements and a second set of sensor electrodes each comprising one or more small subelements. In one embodiment, each of the small subelements may be smaller than any of the large subelements, and the first set of sensor electrodes and the second set of sensor electrodes are formed from a single layer of conductive material. In one embodiment, the surface area of…

BARRIER ELECTRODE DRIVEN BY AN EXCITATION SIGNAL

Granted: September 3, 2015
Application Number: 20150248177
Apparatuses and methods of driving barrier electrodes of a capacitive-sense array with an excitation signal are described. One apparatus includes a capacitance-sensing circuit coupled to a capacitive-sense array including multiple electrodes. The capacitance-sensing circuit includes multiple sensing channels. The capacitance-sensing circuit is operative to measure signals on a first subset of the multiple electrodes using the multiple sensing channels. Each of the sensing channels is…

Stylus Tip Shape

Granted: June 11, 2015
Application Number: 20150160744
Stylus tip configurations may reduce shadow effect of the stylus tip on capacitance measurements by reducing capacitive coupling between undesired portions of the stylus tip and the capacitive sensing surface. Additionally signal-to-noise ratio (SNR) of a stylus on a plurality of capacitance sensing electrodes may be improved by reducing the self capacitance between the stylus tip and the receive electrodes of a mutual capacitance touch screen.

MULTI-CHANNEL, MULTI-BANK MEMORY WITH WIDE DATA INPUT/OUTPUT

Granted: April 30, 2015
Application Number: 20150117091
An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels…

METHOD OF FABRICATING A FERROELECTRIC CAPACITOR

Granted: March 12, 2015
Application Number: 20150072441
Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top…

Active Stylus to Host Data Transmitting Method

Granted: March 5, 2015
Application Number: 20150062094
Apparatus and methods of active stylus to host device data transmitting are described. One method receives, at a stylus, an indication that a host device is performing a first coordinate measurement operation to determine a coordinate of the stylus proximate to a capacitive sense array of the host device. The set of coordinate measurement operations includes a first measurement operation of a first set of electrodes of the capacitive sense array and a second measurement operation of a…

METHODS OF FABRICATING AN F-RAM

Granted: January 1, 2015
Application Number: 20150004718
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS…

SONOS Stack With Split Nitride Memory Layer

Granted: December 25, 2014
Application Number: 20140374813
A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer.…

OVER-VOLTAGE TOLERANT CIRCUIT AND METHOD

Granted: December 18, 2014
Application Number: 20140368960
Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias…

SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES

Granted: December 18, 2014
Application Number: 20140369136
Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage…

ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS

Granted: November 20, 2014
Application Number: 20140340978
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that…

ZERO POWER METERING CIRCUITS, SYSTEMS AND METHODS

Granted: November 6, 2014
Application Number: 20140327553
A system can include a passive wireless interface circuit that generates data from a wireless signal and further includes an energy harvesting circuit that generates first operating power from the wireless signal; a meter interface circuit configured to receive at least one input signal and second operating power from a metering device; logic circuits configured to arbitrate accesses to nonvolatile storage circuits from the passive wireless interface and meter interface circuits using…

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

Granted: October 9, 2014
Application Number: 20140301139
A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude…