Cypress Semiconductor Patent Grants

Reducing sleep current in a capacitance sensing system

Granted: February 21, 2017
Patent Number: 9575606
An apparatus and method of measuring a collective capacitance on a group of capacitive sense elements from at least one of rows or columns of a capacitance sense array when in a first mode, and individually measuring capacitances on each of the rows and columns when in a second mode.

Development, programming, and debugging environment

Granted: February 21, 2017
Patent Number: 9575748
A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program…

Memory devices and methods having multiple address accesses in same cycle

Granted: February 21, 2017
Patent Number: 9576630
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.

Analog-digital converter and control method

Granted: February 21, 2017
Patent Number: 9577654
In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of…

Control circuit

Granted: February 21, 2017
Patent Number: 9578699
Provided is a control circuit capable of suppressing flickering of an LED while preventing degradation of the power efficiency. A control circuit is configured to control electric power to an LED illumination based on a rectified drive voltage, the rectified drive voltage being a drive signal rectified by a rectifier, the drive signal being an AC signal whose phase is controlled by a dimmer including a switching device. The control circuit includes a time period detection part configured…

High reliability non-volatile static random access memory devices, methods and systems

Granted: February 14, 2017
Patent Number: 9570152
A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable nonvolatile element, a first switch element and a second switch element. The first switch element is configured to couple the first programmable nonvolatile element to the first data node during a first read mode of the memory cell. The second switch element is configured to couple the second programmable nonvolatile element to…

Gate fringing effect based channel formation for semiconductor device

Granted: February 14, 2017
Patent Number: 9570458
Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the…

Body position sensing for equipment

Granted: February 7, 2017
Patent Number: 9564062
A device that includes a receiving surface for positioning at least one human body part, multiple capacitive sensor elements disposed within multiple positioning areas on the receiving surface, a sense circuit configured to compare the capacitance measurements of the sensor elements with threshold capacitance values and generate a signal when the capacitance measurements indicate proximity of a human body part on a positioning area, and an indicator configured to generate a notification…

Apparatus and method for rounded ONO formation in a flash memory device

Granted: February 7, 2017
Patent Number: 9564331
A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of…

Dynamically configurable and re-configurable data path

Granted: February 7, 2017
Patent Number: 9564902
An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.

SONOS type stacks for nonvolatile charge trap memory devices and methods to form the same

Granted: January 24, 2017
Patent Number: 9553175
A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming, subsequent to the etching, a charge-trapping layer on the first oxide layer.

System level interconnect with programmable switching

Granted: January 24, 2017
Patent Number: 9553588
Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional…

Fingerprint sensor-compatible overlay

Granted: January 17, 2017
Patent Number: 9547788
A fingerprint sensor-compatible overlay which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. In one embodiment, the overlay is configured to…

Methods of fabricating an F-RAM

Granted: January 17, 2017
Patent Number: 9548348
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS…

Switching circuit

Granted: January 17, 2017
Patent Number: 9548729
A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first…

Asynchronous transceiver for on-vehicle electronic device

Granted: January 10, 2017
Patent Number: 9541990
An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning

Granted: January 10, 2017
Patent Number: 9542588
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…

End-of-life reliability for non-volatile memory cells

Granted: January 10, 2017
Patent Number: 9543017
A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.

Self aligned bump passivation

Granted: January 10, 2017
Patent Number: 9543262
A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.

Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same

Granted: January 3, 2017
Patent Number: 9537511
Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.