Cypress Semiconductor Patent Grants

System-on-chip verification

Granted: March 21, 2017
Patent Number: 9600384
Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the…

Uniform signals from non-uniform patterns of electrodes

Granted: March 14, 2017
Patent Number: 9594462
Apparatuses and methods of sense arrays with non-uniform patterns are described. One capacitive-sense array includes a first set of electrodes and a second set of electrodes. The first set of electrodes intersect the second set of electrodes to form a unit cells each corresponding to an intersection of a pair of electrodes comprising one electrode from the first set and one electrode from the second set. At one of the second set of electrodes includes a non-uniform conductive pattern…

High speed, high voltage tolerant circuits in flash path

Granted: March 14, 2017
Patent Number: 9595332
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process

Granted: March 14, 2017
Patent Number: 9595576
An encapsulated ferroelectric capacitor or ferroelectric memory cell includes encapsulation materials adjacent to a ferroelectric capacitor, a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and an FEO encapsulation layer over the ferroelectric oxide to provide protection from hydrogen induced degradation.

Capacitive sensing button on chip

Granted: March 7, 2017
Patent Number: 9588626
A method and apparatus include a plurality of sensor elements arranged within an integrated circuit package and a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements. The controller is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive signal from a second sensor element of the plurality of sensor elements. The receive signal represents a mutual capacitance of the…

Memory access bases on erase cycle time

Granted: March 7, 2017
Patent Number: 9588695
Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality of indicators for the memory block. The indicator is saved and later retrieved during a read operation.

Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses

Granted: March 7, 2017
Patent Number: 9588881
A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of…

Interrupt latency reduction

Granted: March 7, 2017
Patent Number: 9588916
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.

Asymmetric pass field-effect transistor for non-volatile memory

Granted: March 7, 2017
Patent Number: 9589652
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a…

Split-gate semiconductor device with L-shaped gate

Granted: March 7, 2017
Patent Number: 9589805
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may…

Use disposable gate cap to form transistors, and split gate charge trapping memory cells

Granted: March 7, 2017
Patent Number: 9590079
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a…

Multi-standard compliant USB battery charging scheme with detection of host disconnection in ACA-DOCK mode

Granted: March 7, 2017
Patent Number: 9590441
Techniques for controlling the charging of portable devices are described herein. In an example embodiment, an apparatus comprises a controller coupled to a Universal Serial Bus (USB) port that is configured as a dedicated charging port (DCP). The controller is configured to detect whether a battery-charging (BC) compliant device or a BC non-compliant device is attached to the USB port. When a BC compliant device is detected, the controller controls the charging of the BC compliant…

Control apparatus, and control method for buck-boost power supply with two primary switches

Granted: March 7, 2017
Patent Number: 9590508
A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided. A control apparatus for a buck-boost power supply comprises: a pulse-width modulation (PWM) signal generator configured to generate a PWM signal having a pulse whose pulse width is based on an output voltage; a mode pulse signal generator configured to generate a mode pulse…

Configurable capacitor arrays and switched capacitor circuits

Granted: March 7, 2017
Patent Number: 9590592
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…

Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and a gate oxide in a metal oxide semiconductor (MOS)

Granted: February 28, 2017
Patent Number: 9583501
A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a…

Reducing sleep current in a capacitance sensing system

Granted: February 21, 2017
Patent Number: 9575606
An apparatus and method of measuring a collective capacitance on a group of capacitive sense elements from at least one of rows or columns of a capacitance sense array when in a first mode, and individually measuring capacitances on each of the rows and columns when in a second mode.

Development, programming, and debugging environment

Granted: February 21, 2017
Patent Number: 9575748
A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program…

Memory devices and methods having multiple address accesses in same cycle

Granted: February 21, 2017
Patent Number: 9576630
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.

Analog-digital converter and control method

Granted: February 21, 2017
Patent Number: 9577654
In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of…

Control circuit

Granted: February 21, 2017
Patent Number: 9578699
Provided is a control circuit capable of suppressing flickering of an LED while preventing degradation of the power efficiency. A control circuit is configured to control electric power to an LED illumination based on a rectified drive voltage, the rectified drive voltage being a drive signal rectified by a rectifier, the drive signal being an AC signal whose phase is controlled by a dimmer including a switching device. The control circuit includes a time period detection part configured…