Cypress Semiconductor Patent Grants

Methods, circuits, devices, systems and machine executable code for reading from a non-volatile memory array

Granted: April 25, 2017
Patent Number: 9632867
Disclosed is a method for reading from a non-volatile memory (NVM) device including: retrieving a set of data from an NVM array according to a read sequence for a requested set of logical memory locations received from a host device, detecting errors in the set of data, preparing an error indicator to be output to a host device substantially upon detection of the errors and outputting the error indication in response to a command being received from the host device.

Integrated circuit device with programmable analog subsystem

Granted: April 25, 2017
Patent Number: 9634667
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC…

Hydrogen barriers in a copper interconnect process

Granted: April 18, 2017
Patent Number: 9624094
A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen;…

Type-C connector subsystem

Granted: April 18, 2017
Patent Number: 9625988
A Universal Serial Bus (USB) Type-C connector subsystem is described herein. An integrated circuit (IC) chip device includes a Universal Serial Bus (USB) Type-C subsystem. The USB Type-C subsystem is to operate an Ra termination circuit that consumes no more than a first predetermined amount of current after the Ra termination circuit is applied to a Vconn line of the Type-C subsystem, or to operate a standby reference circuit in a low power mode of the device to perform detection on a…

Systems, methods, and devices for parallel read and write operations

Granted: April 18, 2017
Patent Number: 9627016
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to…

Systems, methods, and apparatus for memory cells with common source lines

Granted: April 18, 2017
Patent Number: 9627073
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to…

Ball grid structure

Granted: April 18, 2017
Patent Number: 9627306
An apparatus includes a contact grid array disposed on a substrate in a non-orthogonal row-column format with connection elements arranged in a hexagonal configuration. The contact grid array has an orientation based, at least in part, on an area available for the contact grid array on the substrate. A method to determine the orientation of the contact grid array includes identifying the area available for a contact grid array on a substrate and determining the orientation for the…

Authentication for recognition systems

Granted: April 11, 2017
Patent Number: 9619645
Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.

Split voltage non-volatile latch cell

Granted: April 11, 2017
Patent Number: 9620225
A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline…

Embedded SONOS based memory cells

Granted: April 11, 2017
Patent Number: 9620516
Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first…

Methods and apparatus to detect a conductive object

Granted: April 4, 2017
Patent Number: 9612265
A method and apparatus scan a first capacitive sensor element that is located in a first scan region for a presence of a conductive object and then scan a second capacitive sensor element that is located in a second scan region for the presence of the conductive object. The scan of the first capacitive sensor element includes applying a ground voltage to a ground element through the second capacitive sensor element, the ground element located in the first scan region.

Dynamically reconfigurable analog routing circuits and methods for system on a chip

Granted: April 4, 2017
Patent Number: 9612987
An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined…

Charge-trap NOR with silicon-rich nitride as a charge trap layer

Granted: April 4, 2017
Patent Number: 9614105
A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT-NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device.

Protecting circuit and integrated circuit

Granted: April 4, 2017
Patent Number: 9614366
Described herein are a protecting circuit and an integrated circuit capable of discharging electric current sufficient for an input voltage having a large time variation while suppressing power consumption. The protecting circuit includes: a first shunt circuit including a first shunt pathway connected to an input terminal, the first shunt circuit being configured to have a relatively low discharge capacity of the first shunt pathway and a relatively long response time; a second shunt…

Multi-bit non-volatile random-access memory cells

Granted: March 28, 2017
Patent Number: 9607695
Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may…

Negative high voltage hot switching circuit

Granted: March 28, 2017
Patent Number: 9608615
A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain…

System-on-chip verification

Granted: March 21, 2017
Patent Number: 9600384
Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the…

Uniform signals from non-uniform patterns of electrodes

Granted: March 14, 2017
Patent Number: 9594462
Apparatuses and methods of sense arrays with non-uniform patterns are described. One capacitive-sense array includes a first set of electrodes and a second set of electrodes. The first set of electrodes intersect the second set of electrodes to form a unit cells each corresponding to an intersection of a pair of electrodes comprising one electrode from the first set and one electrode from the second set. At one of the second set of electrodes includes a non-uniform conductive pattern…

High speed, high voltage tolerant circuits in flash path

Granted: March 14, 2017
Patent Number: 9595332
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process

Granted: March 14, 2017
Patent Number: 9595576
An encapsulated ferroelectric capacitor or ferroelectric memory cell includes encapsulation materials adjacent to a ferroelectric capacitor, a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and an FEO encapsulation layer over the ferroelectric oxide to provide protection from hydrogen induced degradation.