Cypress Semiconductor Patent Grants

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

Granted: July 25, 2017
Patent Number: 9716153
Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on…

Fingerprint sensor pattern

Granted: July 11, 2017
Patent Number: 9704012
An example sensor array includes a first electrode disposed in a first layer, multiple second electrodes disposed in a second layer, and multiple third electrodes disposed outside of the first layer. The second electrodes are galvanically isolated from the first electrode and the third electrodes. In a plan view of the fingerprint sensor array, an area of each third electrode is located within an area of the first electrode.

High voltage architecture for non-volatile memory

Granted: July 11, 2017
Patent Number: 9704585
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

Transceiver for communication and method for controlling communication

Granted: July 11, 2017
Patent Number: 9705697
An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low…

Integrated circuit including parametric analog elements

Granted: July 4, 2017
Patent Number: 9697312
A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further…

High speed serial peripheral interface memory subsystem

Granted: July 4, 2017
Patent Number: 9697872
A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses…

Digital-to-analog converter with a sample and hold circuit and a continuous-time programmable block

Granted: June 27, 2017
Patent Number: 9692442
A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in…

Tape chip on lead using paste die attach material

Granted: June 13, 2017
Patent Number: 9679831
According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a…

Switching circuit

Granted: June 13, 2017
Patent Number: 9680465
A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The…

Temperature detection circuit and temperature measurement circuit

Granted: June 6, 2017
Patent Number: 9671293
A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the…

Buried hard mask for embedded semiconductor device patterning

Granted: June 6, 2017
Patent Number: 9673206
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device comprises a first region, a second region, a first polysilicon region, and a second polysilicon region. The first polysilicon region is formed over the first and second regions of the semiconductor device. Portions of the first and polysilicon layers that are uncovered by either of a first mask and a second…

Integration of a memory transistor into high-k, metal gate CMOS process flow

Granted: June 6, 2017
Patent Number: 9673211
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric…

Access methods and circuits for memory devices having multiple banks

Granted: May 30, 2017
Patent Number: 9666255
A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that…

Non-volatile memory with silicided bit line contacts

Granted: May 30, 2017
Patent Number: 9666591
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density…

Systems and methods for starting up analog circuits

Granted: May 30, 2017
Patent Number: 9667240
Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled…

Systems, methods, and devices for bootstrapped power circuits

Granted: May 23, 2017
Patent Number: 9658632
Systems, methods, and devices are disclosed for implementing a bootstrapped power circuit. Devices may include a controller configured to generate an output signal. Devices may include a power converter configured to receive the output signal, configured to store an amount of energy in response to receiving the output signal, and further configured to release the amount of energy in response to detecting a change in the output signal. Devices may include a switch configured to be toggled…

Single layer sensor pattern

Granted: May 23, 2017
Patent Number: 9658726
A capacitive sensor array comprises large sensor electrodes and small sensor electrodes formed from a single layer of conductive material. Each sensor electrode of a first set of small sensor electrodes is electrically connected to a first pad. A first axis crosses two or more of the sensor electrodes of the first set of small sensor electrodes, and each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the large sensor…

Partially filled contact and trace layout

Granted: May 16, 2017
Patent Number: 9651812
An apparatus including a first layer formed from a first conductive material having a first coefficient of thermal expansion and a second layer, coupled to the first layer, the second layer formed from a second conductive material having a second coefficient of thermal expansion, where the second layer is partially filled.

Low-power touch button sensing system

Granted: May 16, 2017
Patent Number: 9652015
A capacitance sensing circuit receives an application of a power supply. The capacitance sensing circuit controls a switch circuit to connect the power supply to a processing device responsive to the application of the power supply. The capacitance sensing circuit receives, via a control interface and from the processing device, control information to configure the capacitance sensing circuit. The capacitance sensing circuit disconnects the power supply from the processing device…

Systems and methods for downloading code and data into a secure non-volatile memory

Granted: May 16, 2017
Patent Number: 9653004
A method for downloading information into a secure non-volatile memory of a secure embedded device (SED) during a manufacturing or personalization process. The method involves communicating the information and a software program from a device to a temporary storage memory of the SED. The method also involves starting the software program provided to facilitate an initialization of a first key and to facilitate a transfer of at least a portion of the information from the temporary storage…