Exar Patent Applications

ALL DIGITAL BURST-MODE CLOCK AND DATA RECOVERY (CDR)

Granted: May 8, 2014
Application Number: 20140126678
The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

MERGED-STAGE HIGH EFFICIENCY HIGH POWER FACTOR HB-LED DRIVER WITHOUT ELECTROLYTIC CAPACITOR

Granted: May 1, 2014
Application Number: 20140117878
The present application relates to boost-resonant converter for driving high brightness LEDs (HB LED) that incorporates power factor correction (PFC) and does not require a bulky electrolytic capacitor. The new converter incorporates the PFC and the LED supplies into a single stage. The system allows a large voltage ripple across the intermediate energy storage capacitor reducing its value. Constant light output and dimming capability are obtained by variable frequency current control of…

SEQUENTIAL ELECTROSTATIC DISCHARGE (ESD)-PROTECTION EMPLOYING CASCODE NMOS TRIGGERED STRUCTURE

Granted: June 20, 2013
Application Number: 20130155557
An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.

POOLED-RESOURCE ARCHITECTURE WITH ASYNCHRONOUS PACKET-BASED COMMUNICATION

Granted: February 14, 2013
Application Number: 20130038377
A chip includes a pool of blocks. Each block is adapted to implement a communication protocol. A cross-connect configurably connects between the blocks. A configured connection through the cross-connect between a sending block and a receiving block includes a lane with a toggle line and multiple data lines. The receiving block uses the toggle line to determine when valid data is on the data lines. The sending block and receiving block are on different clock domains.

EFFICIENT METHOD TO EXTRACT A LOWER ORDER (LO) OPTICAL CHANNEL DATA UNIT (ODU)j SIGNAL FROM HIGHER ORDER (HO) OPTICAL CHANNEL TRANSPORT UNIT (OTU)k SIGNAL

Granted: January 3, 2013
Application Number: 20130004169
A Higher order (HO) Optical channel Data Unit (ODU)k signal is extracted from an HO Optical channel Transport Unit (OTU)k signal using a first clock at or faster than the OTUk clock. An HO Optical channel Payload Unit OPUk signal is extracted from the HO ODUk signal using the first clock. An Optical channel Data Tributary Unit (ODTU) signal is demultiplexed from the HO OPUk signal using the first clock. The ODTU signal is demapped to a lower order (LO) ODUj signal. The LO ODUj data is…

METHOD TO SOLVE POTENTIAL YIELD LOSS DUE TO METAL MIGRATION TO WIRE ROUTING NETS FROM FIDUCIARY MARKS ON PRODUCT DURING CHEMICAL-MECHANICAL-POLISHING (CMP) PLANARIZATION PROCESSING STEPS

Granted: December 27, 2012
Application Number: 20120326278
A mask for a semiconductor process step includes an indicia section. The indicia section on the mask is used to produce a field of separated polygon elements with a defined negative space in the field providing an indicia.

METHOD FOR MAPPING GENERIC CLIENT SIGNALS INTO A GENERIC FRAMING PROCEDURE (GFP) PATH

Granted: December 27, 2012
Application Number: 20120327786
10 bit words from a client are packed into 64B/65B blocks such that at least some of the blocks have data containing only a portion of at least some of the 10 bit words. The 64B/65B blocks are combined into groups of eight to form superblocks. The superblocks are combined in multiples of five to form a Generic Framing Procedure (GFP) frame such that the GFP frame contains an integer number of complete 10 bit words with no partial 10-bit words.

ETHERNET TAG APPROACH TO SUPPORT NETWORKING TASK OFFLOAD

Granted: December 27, 2012
Application Number: 20120327952
A two chip network adapter is used to implement offloaded networking tasks. The first chip is the main ethernet controller chip. The second chip implements the offloaded tasks. Communication between a host and the second chip is done by adding offload and completion tags to the ethernet frame header of frames associated with the offloaded networking task.

METHOD FOR REMOTE DEVICE PROVISIONING AND INSERTION/EXTRACTION OF OVERHEAD/EOAM DATA FOR VARIOUS PROTOCOLS

Granted: December 27, 2012
Application Number: 20120327958
A device demultiplexes an optical signal to produce a number of client streams for client devices. The device produces overhead packets for the client devices. The overhead packets are sent using a packet interface on the device. The overhead packets are sent to the client devices with a Virtual Local Area Network Identification (VLAN ID) portion of the overhead packets identify a client device of the client devices.

METHOD FOR AGGREGATING MULTIPLE CLIENT SIGNALS INTO A GENERIC FRAMING PROCEDURE (GFP) PATH

Granted: December 27, 2012
Application Number: 20120328288
Used bandwidth counts for each of multiple client streams are maintained. A used bandwidth count for a client stream is increased when data from the client stream is put in a Generic Framing Procedure (GFP) frame onto the GFP path and is decreased once every time period by allocated bandwidth credits value. The used bandwidth count for a client stream is compared with a bandwidth limit before sending data in the client stream in a GFP frame onto the GFP path.

METHOD FOR TRANSPORT AND RECOVERY OF CLIENT CLOCKING ACROSS ASYNCHRONOUS SERVER NETWORKS

Granted: December 27, 2012
Application Number: 20120331176
At a generator, frame events are received indicative of frame boundaries. The amount of client data received between frame events is counted to get a raw count. The raw count is low-pass filtered to get a smoothed value. At a receiver, an indication of the smoothed count is received from the generator; and the indication is smoothed using a low-pass filter and used to produce a client data rate.

DIGITAL PULSE-FREQUENCY MODULATION CONTROLLER FOR SWITCH-MODE POWER SUPPLIES WITH FREQUENCY TARGETING AND ULTRASONIC MODES

Granted: September 6, 2012
Application Number: 20120223691
A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and…

SENSORLESS SELF-TUNING DIGITAL CURRENT PROGRAMMED MODE (CPM) CONTROLLER WITH MULTIPLE PARAMETER ESTIMATION AND THERMAL STRESS EQUALIZATION

Granted: September 6, 2012
Application Number: 20120223692
A multiphase controller for a DC-to-DC power supply includes logic to estimate parameters for multiple phases that provide a combined output at a load. The estimated parameters include a current estimate and an effective resistance estimates for each phase so that a power estimate for each phase can be produced. The logic adjusts the operation of the phases using the power estimate for each phase.

SET-POINT RESOLUTION IMPROVEMENT FOR SWITCH MODE POWER SUPPLIES

Granted: September 6, 2012
Application Number: 20120223849
A Digital-to-Analog Converter (DAC) produces an analog reference value from a first reference input. The analog reference value and an output value are used to produce an analog error signal. An Analog-to-Digital Converter (ADC) converts the analog error signal to a digital value. The ADC has higher level of resolution than the DAC. An error encoder adjusts the digital value to produce a digital error value using a second reference input.

APPARATUS AND METHOD OF DELTA COMPRESSION

Granted: July 19, 2012
Application Number: 20120185612
A method includes aligning a reference window and target window for compression of a target data stream in terms of a reference data stream. The anchors are determined by examining the target data stream and reference data streams. The target data stream is aligned with respect to the reference data streams using the anchors. Pattern matching between the aligned target data stream and reference data stream is done to delta compress the target data stream.

DIGITAL BOOST FEEDBACK VOLTAGE CONTROLLER FOR SWITCH-MODE POWER SUPPLIES USING PULSE-FREQUENCY MODULATION

Granted: June 21, 2012
Application Number: 20120153916
A controller produces high-side and low-side control signals. The high and low-side signals are used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage. A boost feedback charge pump receives the low or high-side signal to increase the charge on a charge pump output capacitor. The controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that control the voltage…

COMMUNICATIONS SYSTEMS WITH SCAN TABLE IDENTIFICATION

Granted: May 3, 2012
Application Number: 20120106568
A communications system, comprising a first device including a first scan table and a second device including a second scan table. The first device is configured to select the first scan table and transmit scan table identification. The second device is configured to receive the scan table identification from the first device and select the second scan table based on the received scan table identification.

REFERENCE VOLTAGE BASED EQUIVALENT SERIES RESISTANCE (ESR) EMULATION FOR CONSTANT ON-TIME (COT) CONTROL OF BUCK REGULATORS

Granted: April 5, 2012
Application Number: 20120081094
The present invention uses a reference voltage that varies within a Pulse Width Modulation (PWM) cycle to generate the PWM signal. This allows for stability in the feedback of Constant On-Time (COT) control for buck controllers when low Equivalent Series Resistance (ESR) capacitors are used as the output capacitor. The reference voltage is adjusted using features of a PWM cycle in a voltage mode without using external inductor current information.

DEJITTER (DESYNCHRONIZE) TECHNIQUE TO SMOOTH GAPPED CLOCK WITH JITTER/WANDER ATTENUATION USING ALL DIGITAL LOGIC

Granted: March 1, 2012
Application Number: 20120051477
Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and…

VIRTUAL BLOCK DEVICE

Granted: November 10, 2011
Application Number: 20110276543
A virtual block device is an interface with applications that appears to the applications as a memory device, such as a standard block device. The virtual block device interacts with additional elements to do data deduplication to files at the block level such that one or more files accessed using the virtual block device have at least one block which is shared by the one or more files.