Exar Patent Grants

Network data prioritizer

Granted: January 10, 2017
Patent Number: 9544242
A data packaging system is programmed to modify or otherwise manage a data stream from a data source prior to transmission to an intended recipient by applying an expressible intent regarding the data stream from the recipient in the form of a recipient signature. A data packager can apply a received recipient signature to modify the data stream based on the contents of the data stream. The modifications to the data stream can include prioritization of portions of the data stream…

All digital burst-mode clock and data recovery (CDR)

Granted: April 28, 2015
Patent Number: 9020087
The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.

Dejitter (desynchronize) technique to smooth gapped clock with jitter/wander attenuation using all digital logic

Granted: October 21, 2014
Patent Number: 8867682
Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and…

Streaming and bulk data transfer transformation with context switching

Granted: October 21, 2014
Patent Number: 8868674
In described embodiments, processing of a data stream, such as a packet stream or flow, associated with data streaming is improved by context switching that employs context history. For each data stream that is transformed through processing, a context is maintained that comprises state information and includes a history and state information that enables the transformation for the data stream. Processing for the data transformation examines currently arriving data and then processes the…

Sequential electrostatic discharge (ESD)-protection employing cascode NMOS triggered structure

Granted: August 19, 2014
Patent Number: 8810981
An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.

Sensorless self-tuning digital current programmed mode (CPM) controller with multiple parameter estimation and thermal stress equalization

Granted: September 17, 2013
Patent Number: 8536842
A multiphase controller for a DC-to-DC power supply includes logic to estimate parameters for multiple phases that provide a combined output at a load. The estimated parameters include a current estimate and an effective resistance estimates for each phase so that a power estimate for each phase can be produced. The logic adjusts the operation of the phases using the power estimate for each phase.

Digital pulse-frequency modulation controller for switch-mode power supplies with frequency targeting and ultrasonic modes

Granted: September 3, 2013
Patent Number: 8525502
A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and…

Reference voltage based equivalent series resistance (ESR) emulation for constant on-time (COT) control of buck regulators

Granted: July 2, 2013
Patent Number: 8476882
The present invention uses a reference voltage that varies within a Pulse Width Modulation (PWM) cycle to generate the PWM signal. This allows for stability in the feedback of Constant On-Time (COT) control for buck controllers when low Equivalent Series Resistance (ESR) capacitors are used as the output capacitor. The reference voltage is adjusted using features of a PWM cycle in a voltage mode without using external inductor current information.

Digital boost feedback voltage controller for switch-mode power supplies using pulse-frequency modulation

Granted: January 29, 2013
Patent Number: 8362756
A controller produces high-side and low-side control signals. The high and low-side signals are used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage. A boost feedback charge pump receives the low or high-side signal to increase the charge on a charge pump output capacitor. The controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that control the voltage…

Digital control method for improving heavy-to-light (step down) load transient response of switch mode power supplies

Granted: September 25, 2012
Patent Number: 8274264
A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.

Methodology for storing and updating on-chip revision level

Granted: June 26, 2012
Patent Number: 8209654
Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.

System and method for data deduplication

Granted: June 19, 2012
Patent Number: 8205065
A system for deduplicating data comprises a card operable to receive at least one data block and a processor on the card that generates a hash for each data block. The system further comprises a first module that determines a processing status for the hash and a second module that discards duplicate hashes and their data blocks and writes unique hashes and their data blocks to a computer readable medium. In one embodiment, the processor also compresses each data block using a compression…

Output current and input power regulation with a power converter

Granted: June 5, 2012
Patent Number: 8193795
A power converter circuit senses the output voltage (Vo) and controls the converter's duty cycle (d1) to provide a steady output current (Io) or input power (Pin) in each switching cycle (T). During an initial period (Tramp), the controller provides a possibly smaller target current (Iramp) to reduce the system stress while the output voltage rises to a suitable value (InitVtar).

Methods, systems and computer program products for packet ordering for parallel packet transform processing

Granted: May 29, 2012
Patent Number: 8189591
Packets are processed while maintaining a sequence of the packets. Packets are received and a sequence identifier assigned to the packets. The sequence identifier specifies a serial order associated with the packet. The packets are provided to a plurality of parallel packet transform processors and the packets are processed utilizing the packet transform processors. The processed packets are ordered based on the sequence identifier of the packets. The packets may be evaluated to classify…

ESR zero estimation and auto-compensation in digitally controlled buck converters

Granted: February 14, 2012
Patent Number: 8115459
One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the…

Open-drain output buffer for single-voltage-supply CMOS

Granted: January 17, 2012
Patent Number: 8098090
An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching…

Self-tuning digital current estimator for low-power switching converters

Granted: December 27, 2011
Patent Number: 8085024
A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator.

Glue-logic based method and system for minimizing losses in oversampled digitally controlled DC-DC converters

Granted: December 20, 2011
Patent Number: 8081041
A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.

Low-voltage CMOS space-efficient 15 KV ESD protection for common-mode high-voltage receivers

Granted: June 28, 2011
Patent Number: 7969697
An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each…

Multi-channel digital pulse width modulator (DPWM)

Granted: March 29, 2011
Patent Number: 7915938
A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple…