GSI Technology Patent Applications

SYSTEMS AND METHODS INVOLVING PSEUDO COMPLEMENTARY OUTPUT BUFFER CIRCUITRY/SCHEMES, POWER NOISE REDUCTION AND/OR OTHER FEATURES

Granted: March 2, 2017
Application Number: 20170063372
A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may b e coupled to an output of the second inverter on a first terminal and a ground on a second terminal,…

Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs

Granted: October 9, 2014
Application Number: 20140304463
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide…

SYSTEMS AND METHODS OF PIPELINED OUTPUT LATCHING INVOLVING SYNCHRONOUS MEMORY ARRAYS

Granted: September 25, 2014
Application Number: 20140286083
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the…

SYSTEMS AND METHODS INVOLVING DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND/OR OPERATION

Granted: September 25, 2014
Application Number: 20140289440
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides…

SYSTEMS AND METHODS INVOLVING DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND/OR OPERATION INCLUDING DATA SIGNALS GROUPED INTO 10 BITS AND/OR OTHER FEATURES

Granted: September 25, 2014
Application Number: 20140289460
Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI…

LASER ADJUSTABLE DEPTH MARK SYSTEM AND METHOD

Granted: July 16, 2009
Application Number: 20090179015
A system and method for adjustable laser mark depth is provided. In one embodiment, the system is used in Nd—YAG laser marker for wafer processing in the semiconductor industry, with smart control of the mark depth and expanded work range between the deep mark and the light mark.

SYSTEM AND METHOD FOR REFRESHING A DRAM DEVICE

Granted: February 7, 2008
Application Number: 20080031069
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the…