GSI Technology Patent Grants

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

Granted: May 4, 2021
Patent Number: 10998040
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

In memory matrix multiplication and its usage in neural networks

Granted: May 4, 2021
Patent Number: 10997275
A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a…

Computational memory cell and processing array device using complementary exclusive or memory cells

Granted: March 23, 2021
Patent Number: 10958272
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

One by one selection of items of a set

Granted: March 23, 2021
Patent Number: 10956432
A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly…

Precise exponent and exact softmax computation

Granted: March 16, 2021
Patent Number: 10949766
A method for an associative memory device includes dividing a multi-bit mantissa A of a number X to a plurality of smaller partial mantissas Aj, offline calculating a plurality of partial exponents F(Aj) for each possible value of each partial mantissa Aj and storing the plurality of partial exponents F(Aj) in a look up table (LUT) of the associative memory device. A system includes an associative memory array to store a plurality of partial mantissas Ai of a mantissa A of a number X and…

Ultra low VDD memory cell with ratioless write port

Granted: March 9, 2021
Patent Number: 10943648
An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Method for min-max computation in associative memory

Granted: March 9, 2021
Patent Number: 10942736
A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory array and performing a horizontal bit-wise Boolean operation on rows of the associative memory array to produce an extreme SOR (ESOR) having the extreme value. A system for finding an extreme value includes an associative memory array to store the…

Processing array device that performs one cycle full adder operation and bit line read/write logic features

Granted: February 23, 2021
Patent Number: 10930341
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Finding K extreme values in constant processing time

Granted: February 23, 2021
Patent Number: 10929751
A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row…

Error detecting memory device

Granted: February 16, 2021
Patent Number: 10922169
A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns. The array includes a plurality of word lines, first bit lines and second bit lines, a NOR gate per column Each word line activates memory cells in a row and thereby establishes an activated row. First bit lines and second bit lines connect memory cells in columns, each first bit line provides the result of a Boolean AND operation between data stored in the first activated row…

Massively parallel, associative multiplier accumulator

Granted: January 12, 2021
Patent Number: 10891991
An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder. The memory array has a multiplicity of rows and columns, each column being divided into a plurality of bit line processors and each bit line processor operating on its associated pair of input values. The multi-bit multiplier utilizes each bit line processor to multiply the associated pair of input values in each bit line processor to generate multiplication results. The…

Results processing circuits and methods associated with computational memory cells

Granted: January 12, 2021
Patent Number: 10891076
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Processing array device that performs one cycle full adder operation and bit line read/write logic features

Granted: December 29, 2020
Patent Number: 10877731
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Orthogonal data transposition system and method during data transfers to/from a processing array

Granted: December 8, 2020
Patent Number: 10860320
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.

Computational memory cell and processing array device using memory cells

Granted: December 8, 2020
Patent Number: 10860318
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Computational memory cell and processing array device with ratioless write port

Granted: December 1, 2020
Patent Number: 10854284
A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Write data processing circuits and methods associated with computational memory cells

Granted: November 24, 2020
Patent Number: 10847213
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of ā€œnā€ bit lines.

Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers

Granted: November 24, 2020
Patent Number: 10847212
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the…

Sparse matrix multiplication in associative memory device

Granted: November 24, 2020
Patent Number: 10846365
A method for use in an associative memory device when multiplying by a sparse matrix includes storing only non-zero elements of the sparse matrix in the associative memory device as multiplicands. The storing includes locating the non-zero elements in computation columns of the associative memory device according to linear algebra rules along with their associated multiplicands such that a multiplicand and a multiplier of each multiplication operation to be performed are stored in a same…

Non-volatile in-memory computing device

Granted: November 10, 2020
Patent Number: 10832746
Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including…