Integrated Device Tech Patent Grants

Apparatus, system, and method for detecting a foreign object in an inductive wireless power transfer system via coupling coefficient measurement

Granted: January 24, 2017
Patent Number: 9551805
An inductive wireless power device comprises a transmitter configured to generate an electromagnetic field to a coupling region for wireless power transfer to a receiver, and control logic configured to determine a coupling coefficient of the wireless power transfer when the receiver is within the coupling region. The control logic also determines a presence of a foreign object within the coupling region responsive to a comparison of the determined coupling coefficient and an expected…

Memory includes transmitter for data synchronization transmission after a mode switch and method thereof

Granted: January 24, 2017
Patent Number: 9552870
An apparatus includes a memory and a circuit. The memory may have a transmitter. The memory may be configured to (a) train transmit parameters of the transmitter that synchronize transmission of data with a clock signal while in a first mode, (b) save the transmit parameters in response to a command received while in the first mode, and (c) transmit additional data while in a second mode using the transmit parameters learned while in the first mode. The circuit may have a receiver in…

Apparatus, system, and method for detecting a foreign object in an inductive wireless power transfer system based on input power

Granted: January 24, 2017
Patent Number: 9553485
An inductive wireless power transfer system comprises a transmitter configured to generate an electromagnetic field to a coupling region for providing energy transfer to a wireless power receiving apparatus. The transmitter includes control logic configured to determine a power component of the transmitter, and determine a presence of a foreign object within the coupling region in response to a comparison of the power component and a desired threshold for the power component. Related…

Crystal-less jitter attenuator

Granted: January 24, 2017
Patent Number: 9553570
An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional…

Methods and systems for analog-to-digital conversion (ADC) using an ultra small capacitor array with full range and sub-range modes

Granted: January 24, 2017
Patent Number: 9553602
Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal…

Method and apparatus utilizing packet segment compression parameters for compression in a communication system

Granted: January 24, 2017
Patent Number: 9553954
A method and apparatus for compressing data in a communication system by receiving uncompressed packet at a compressor of the communication system, segmenting the packet into a plurality of packet segments, estimating packet segment compression parameters for each of the plurality of packet segments and compressing the packet segments utilizing one or more of the estimated packet segment compression parameters that are estimated and adjusted based upon the signal characteristics of the…

Single-ended signal equalization with a programmable 1-tap decision feedback equalizer

Granted: January 10, 2017
Patent Number: 9542991
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) receive a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel, (ii) slice a previous input value of said sequence of input values to generate a previous output value, (iii) slice a current input value of said sequence of input values to generate a current output value, and (iv) present said current output value on a…

Multi-stage frequency dividers having duty cycle correction circuits therein

Granted: January 10, 2017
Patent Number: 9543960
A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by…

High speed, low power, isolated multiplexer

Granted: December 20, 2016
Patent Number: 9525408
Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by…

Apparatuses and methods for over-temperature protection of energy storage devices

Granted: December 6, 2016
Patent Number: 9515510
A charging system includes a temperature sensor to generate a temperature signal responsive to a temperature of an energy storage device. A circuit temperature sensor generates a circuit temperature signal responsive to a temperature of a semiconductor device. A charge adjuster generates a desired current signal responsive to the temperature signal and the circuit temperature signal. A comparator compares a charge-current level signal to the desired current signal to generate a charge…

Temperature detection method and device with improved accuracy and conversion time

Granted: November 29, 2016
Patent Number: 9506817
Temperature accuracy is improved, conversion gain is increased without increasing current density and parasitic resistance errors and other problems with conventional bandgap reference temperature sensors are eliminated by generating a signal proportional to temperature from four samples, where the signal is defined as a difference between a first difference and a second difference, the first difference comprising a difference between the second sample and the first sample, the second…

Method and apparatus for using tester channel as device power supply

Granted: November 22, 2016
Patent Number: 9500707
A method and apparatus for using a tester channel as device power have been disclosed. By utilizing a tester channel output as an input, a voltage and current driver are used to boost the input which is followed by a current to voltage converter which can be used as a device power supply for a device under test. Additional tester channels may be used to sense and force voltages, measure currents, supply output voltage, and relay control, etc. for changing operation.

Integrated circuit devices having oscillator circuits therein that support fixed frequency generation over process-voltage-temperature (PVT) variations

Granted: November 22, 2016
Patent Number: 9503059
Oscillator circuits that support highly accurate fixed frequency generation over process, voltage and temperature (PVT) variations include a reference voltage generator, which is configured to generate a reference voltage across a resistor (e.g., high precision poly-resistor) therein. An auto-zeroing comparator is provided, which is configured to generate a differential clock signal (e.g., Ck, Ckb) at an output thereof. First and second switched capacitor circuits are further provided,…

Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM)

Granted: November 15, 2016
Patent Number: 9495285
The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the…

Low power driver with programmable output impedance

Granted: November 8, 2016
Patent Number: 9490805
A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for…

Integrated circuits having multiple digitally-controlled oscillators (DCOs) therein that are slaved to the same loop filter

Granted: November 8, 2016
Patent Number: 9490828
A phase-locked loop (PLL) integrated circuit includes multiple digitally-controlled oscillators (DCOs), which are slaved to the same feedback loop filter. This PLL includes a frequency control circuit, which is configured to generate a control signal and is responsive to a first periodic reference signal (e.g., REFCLK). The plurality of DCOs include a corresponding plurality of independently-programmable fractional dividers, which are configured to generate a respective plurality of…

Long-distance RapidIO packet delivery

Granted: November 1, 2016
Patent Number: 9485053
The present invention provides a RapidIO device that includes a switch fabric and a port coupled to the switch fabric. The port is configured to establish a LP-Serial link with RapidIO endpoints, add packet headers having the same acknowledgement identifier to a plurality of contiguous packets and generate a link cyclical redundancy check value for the plurality of contiguous packets having the same acknowledgement identifier, the link cyclical redundancy check code computed to include…

Method and apparatus for controlling error and identifying bursts in a data compression system

Granted: November 1, 2016
Patent Number: 9485688
The method and apparatus of the present invention provides for the compression and decompression of data bursts wherein the propagation of synchronization errors is limited to a desired number of signal samples and the start of a burst boundary is identified. In accordance with the present invention, a method and apparatus are provided for compressing data in a communication system by receiving data bursts comprising a plurality of uncompressed data packets at a compressor of the…

Integrated circuit device substrates having packaged inductors thereon

Granted: October 25, 2016
Patent Number: 9478599
An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and…

Self-calibrating fractional divider circuits

Granted: October 25, 2016
Patent Number: 9479177
A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REFHF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC)…