Integrated Device Tech Patent Grants

Single-ended memory signal equalization at power up

Granted: March 7, 2017
Patent Number: 9589626
An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power…

High-speed programmable frequency divider with 50% output duty cycle

Granted: March 7, 2017
Patent Number: 9590637
A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock…

Dual mode clock using a common resonator and associated method of use

Granted: February 28, 2017
Patent Number: 9581973
An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock…

Single-ended signal slicer with a wide input voltage range

Granted: February 28, 2017
Patent Number: 9583155
An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to (i) reduce a current value in a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel to generate a version of the current value, and (ii) reduce a first reference voltage to generate a second reference voltage. The second circuit may be configured to slice the current value with respect to the first reference…

Receiver equalization circuit with cross coupled transistors and/or RC impedance

Granted: February 28, 2017
Patent Number: 9583175
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory controller, (b) buffer read signals presented on the data bus and (c) condition the write signals. The conditioning may be implemented by (i) converting the write signals to a first differential write signal on a first differential write line and a second differential write signal on a second…

Wireless power system

Granted: February 21, 2017
Patent Number: 9577438
The present disclosure relates wireless power transfer. In some embodiments, DC power is received through one or more inductors and switched to provide alternating current through a TX coil with a pair of power FETs coupled between opposite sides of the TX coil and ground such that current flows through one of the pair of FETs at a time. In some embodiments, the pair of FETs can be driven in adaptive resonant mode to operate at a resonance. In some embodiments, the pair of FETs are…

Apparatus, system, and method for detecting a foreign object in an inductive wireless power transfer system via coupling coefficient measurement

Granted: January 24, 2017
Patent Number: 9551805
An inductive wireless power device comprises a transmitter configured to generate an electromagnetic field to a coupling region for wireless power transfer to a receiver, and control logic configured to determine a coupling coefficient of the wireless power transfer when the receiver is within the coupling region. The control logic also determines a presence of a foreign object within the coupling region responsive to a comparison of the determined coupling coefficient and an expected…

Memory includes transmitter for data synchronization transmission after a mode switch and method thereof

Granted: January 24, 2017
Patent Number: 9552870
An apparatus includes a memory and a circuit. The memory may have a transmitter. The memory may be configured to (a) train transmit parameters of the transmitter that synchronize transmission of data with a clock signal while in a first mode, (b) save the transmit parameters in response to a command received while in the first mode, and (c) transmit additional data while in a second mode using the transmit parameters learned while in the first mode. The circuit may have a receiver in…

Apparatus, system, and method for detecting a foreign object in an inductive wireless power transfer system based on input power

Granted: January 24, 2017
Patent Number: 9553485
An inductive wireless power transfer system comprises a transmitter configured to generate an electromagnetic field to a coupling region for providing energy transfer to a wireless power receiving apparatus. The transmitter includes control logic configured to determine a power component of the transmitter, and determine a presence of a foreign object within the coupling region in response to a comparison of the power component and a desired threshold for the power component. Related…

Crystal-less jitter attenuator

Granted: January 24, 2017
Patent Number: 9553570
An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional…

Methods and systems for analog-to-digital conversion (ADC) using an ultra small capacitor array with full range and sub-range modes

Granted: January 24, 2017
Patent Number: 9553602
Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal…

Method and apparatus utilizing packet segment compression parameters for compression in a communication system

Granted: January 24, 2017
Patent Number: 9553954
A method and apparatus for compressing data in a communication system by receiving uncompressed packet at a compressor of the communication system, segmenting the packet into a plurality of packet segments, estimating packet segment compression parameters for each of the plurality of packet segments and compressing the packet segments utilizing one or more of the estimated packet segment compression parameters that are estimated and adjusted based upon the signal characteristics of the…

Single-ended signal equalization with a programmable 1-tap decision feedback equalizer

Granted: January 10, 2017
Patent Number: 9542991
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) receive a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel, (ii) slice a previous input value of said sequence of input values to generate a previous output value, (iii) slice a current input value of said sequence of input values to generate a current output value, and (iv) present said current output value on a…

Multi-stage frequency dividers having duty cycle correction circuits therein

Granted: January 10, 2017
Patent Number: 9543960
A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by…

High speed, low power, isolated multiplexer

Granted: December 20, 2016
Patent Number: 9525408
Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by…

Apparatuses and methods for over-temperature protection of energy storage devices

Granted: December 6, 2016
Patent Number: 9515510
A charging system includes a temperature sensor to generate a temperature signal responsive to a temperature of an energy storage device. A circuit temperature sensor generates a circuit temperature signal responsive to a temperature of a semiconductor device. A charge adjuster generates a desired current signal responsive to the temperature signal and the circuit temperature signal. A comparator compares a charge-current level signal to the desired current signal to generate a charge…

Temperature detection method and device with improved accuracy and conversion time

Granted: November 29, 2016
Patent Number: 9506817
Temperature accuracy is improved, conversion gain is increased without increasing current density and parasitic resistance errors and other problems with conventional bandgap reference temperature sensors are eliminated by generating a signal proportional to temperature from four samples, where the signal is defined as a difference between a first difference and a second difference, the first difference comprising a difference between the second sample and the first sample, the second…

Method and apparatus for using tester channel as device power supply

Granted: November 22, 2016
Patent Number: 9500707
A method and apparatus for using a tester channel as device power have been disclosed. By utilizing a tester channel output as an input, a voltage and current driver are used to boost the input which is followed by a current to voltage converter which can be used as a device power supply for a device under test. Additional tester channels may be used to sense and force voltages, measure currents, supply output voltage, and relay control, etc. for changing operation.

Integrated circuit devices having oscillator circuits therein that support fixed frequency generation over process-voltage-temperature (PVT) variations

Granted: November 22, 2016
Patent Number: 9503059
Oscillator circuits that support highly accurate fixed frequency generation over process, voltage and temperature (PVT) variations include a reference voltage generator, which is configured to generate a reference voltage across a resistor (e.g., high precision poly-resistor) therein. An auto-zeroing comparator is provided, which is configured to generate a differential clock signal (e.g., Ck, Ckb) at an output thereof. First and second switched capacitor circuits are further provided,…

Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM)

Granted: November 15, 2016
Patent Number: 9495285
The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the…