Integrated Silicon Solution Patent Grants

Low power high speed program method for multi-time programmable memory device

Granted: January 10, 2017
Patent Number: 9543016
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present…

DRAM error correction event notification

Granted: December 27, 2016
Patent Number: 9529667
A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the…

Auto low current programming method without verify

Granted: December 6, 2016
Patent Number: 9514806
A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases…

Resistive memory device implementing selective memory cell refresh

Granted: November 15, 2016
Patent Number: 9496030
A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with…

High speed sequential read method for flash memory

Granted: November 15, 2016
Patent Number: 9496046
A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is…

Resistive memory device implementing selective memory cell refresh

Granted: June 21, 2016
Patent Number: 9373393
A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with…

Circuit and method for testing memory devices

Granted: June 21, 2016
Patent Number: 9373417
The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines. The circuit comprises: a test pattern generator coupled to a first portion of the plurality of address lines to receive test data, and configured to store the test data and to generate a write test vector and a read test vector according to the…

Flash memory device with sense-amplifier-bypassed trim data read

Granted: May 24, 2016
Patent Number: 9349472
A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured…

Erase algorithm for flash memory

Granted: May 10, 2016
Patent Number: 9336893
A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the…

Method for improving sensing margin of resistive memory

Granted: April 26, 2016
Patent Number: 9324426
A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the…

Glitch free input transition detector

Granted: April 19, 2016
Patent Number: 9319038
A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Reference current circuit with temperature coefficient correction

Granted: March 22, 2016
Patent Number: 9293215
A flash memory device uses a pair of parallely connected NMOS transistors with different voltage ratings to generate the reference current for the sense amplifier used in the read out operations. The reference current thus generated is temperature compensated with zero or near-zero temperature coefficient. In some embodiments, the pair of parallely connected NMOS transistors includes a high voltage NMOS transistor and a low voltage NMOS transistor or NMOS transistors with different gate…

Circuit and method for controlling internal test mode entry of an ASRAM chip

Granted: March 15, 2016
Patent Number: 9287008
A circuit and method for controlling internal test mode entry of an Asynchronous Static Random Access Memory (ASRAM) chip wherein the circuit includes an address code comparator for detecting whether address codes inputted via an address bus of the ASRAM chip match a predefined validation code; a test mode detector for determining whether to let the ASRAM chip enter into an internal test mode; a test mode clock generator for generating a clock signal for the test mode decoder; and a test…

Memory device implementing reduced ECC overhead

Granted: March 8, 2016
Patent Number: 9280418
A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel…

Methods for erasing, reading and programming flash memories

Granted: February 16, 2016
Patent Number: 9263141
The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of ?7V˜?10V. When a read operation is performed on the flash memory, for a…

Reference current generation in resistive memory device

Granted: December 1, 2015
Patent Number: 9202561
A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias…

Memory device with multiple cell write for a single input-output in a single write cycle

Granted: November 3, 2015
Patent Number: 9177650
A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of…

Address transition detecting circuit

Granted: October 27, 2015
Patent Number: 9171609
The address transition detecting circuit includes two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating modules have a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two…

Auto low current programming method without verify

Granted: August 25, 2015
Patent Number: 9117549
A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases…

Erase algorithm for flash memory

Granted: August 4, 2015
Patent Number: 9099192
A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the…