Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments
Granted: February 14, 2023
Patent Number:
11580014
A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary…
System and method for training neural networks with errors
Granted: February 7, 2023
Patent Number:
11574194
A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data on which to train a neural network comprising at least one quantized layer and performs a set of training iterations to train weights for the neural network. Each training iteration of the set of training iterations includes stochastically writing…
System and method for classifying data using neural networks with errors
Granted: January 31, 2023
Patent Number:
11568222
A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using…
Methods of manufacture precessional spin current magnetic tunnel junction devices
Granted: January 3, 2023
Patent Number:
11545620
A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Ru) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.
Selector transistor with continuously variable current drive
Granted: January 3, 2023
Patent Number:
11545524
A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane…
Three-dimensional (3D) magnetic memory devices comprising a magnetic tunnel junction (MTJ) having a metallic buffer layer
Granted: September 27, 2022
Patent Number:
11456410
A magnetic memory device comprises a cylindrical core and a plurality of layers surrounding the core. The plurality of layers include a metallic buffer layer, a ferromagnetic storage layer, a barrier layer, and a ferromagnetic reference layer. The cylindrical core, the metallic buffer layer, the ferromagnetic storage layer, the barrier layer, and the ferromagnetic reference layer collectively form a magnetic tunnel junction. A magnetization of the ferromagnetic layer storage parallels an…
Selector transistor with metal replacement gate wordline
Granted: September 13, 2022
Patent Number:
11444123
A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure…
Arbitration control for pseudostatic random access memory device
Granted: September 13, 2022
Patent Number:
11442875
An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a set-reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a…
Magnetic tunnel junction element with Ru hard mask for use in magnetic random-access memory
Granted: May 10, 2022
Patent Number:
11329100
A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a…
Method for manufacturing a magnetic random-access memory device using post pillar formation annealing
Granted: May 10, 2022
Patent Number:
11329217
A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both…
Magnetic memory chip having nvm class and SRAM class MRAM elements on the same chip
Granted: May 10, 2022
Patent Number:
11329099
A magnetic random access memory chip having magnetic memory elements with different performance characteristics formed on the same chip. The magnetic memory elements can be magnetic random access memory elements. The memory chip can have a first set of magnetic random access chips having a first set of physical and performance characteristics formed in a first area of the sensor and a second set of magnetic random access chips having a second set of performance characteristics formed in…
DRAM with selective epitaxial transistor and buried bitline
Granted: May 10, 2022
Patent Number:
11329048
A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by…
Sense amplifier circuit for preventing read disturb
Granted: May 10, 2022
Patent Number:
11328771
A sense amplifier circuit implements a sense scheme using sense amplifier feedback control to disconnect the bit lines from the sense circuit during the read operation after the bit line signals are sensed. In this manner, read disturbance during the read operation is prevented. In some embodiments, the sense amplifier circuit includes a pair of pass gates to couple a pair of differential bit lines to a sense circuit. The sense amplifier circuit further includes a feedback control…
DRAM with selective epitaxial cell transistor
Granted: April 12, 2022
Patent Number:
11302697
A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the…
Compact and efficient CMOS inverter
Granted: April 12, 2022
Patent Number:
11302586
A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first…
Precessional spin current structure for magnetic random access memory with novel capping materials
Granted: March 22, 2022
Patent Number:
11283010
A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and…
Precessional spin current structure with nonmagnetic insertion layer for MRAM
Granted: March 8, 2022
Patent Number:
11271149
A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second…
High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices
Granted: March 1, 2022
Patent Number:
11264557
A method for manufacturing a magnetic random access memory element having increased retention and low resistance area product (RA). A MgO layer is deposited to contact a magnetic free layer of the memory element. The MgO layer is deposited in a sputter deposition chamber using a DC power and a Mg target to deposit Mg. The deposition of Mg is periodically stopped and oxygen introduced into the deposition chamber. This process is repeated a desired number of times, resulting in a…
Perpendicular magnetic tunnel junction memory cells having vertical channels
Granted: January 11, 2022
Patent Number:
11222970
A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of…
Memory inspecting method and memory inspecting system
Granted: December 7, 2021
Patent Number:
11195592
A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention…
