Intel Patent Applications

HIGH PERFORMANCE TRANSIENT UNIFORM COOLING SOLUTION FOR THERMAL COMPRESSION BONDING PROCESS

Granted: January 19, 2017
Application Number: 20170014957
Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.

TUNGSTEN ALLOYS IN SEMICONDUCTOR DEVICES

Granted: January 19, 2017
Application Number: 20170018506
Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

THROUGH-BODY VIA LINER DEPOSITION

Granted: January 19, 2017
Application Number: 20170018509
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the…

TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS

Granted: January 19, 2017
Application Number: 20170018543
Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices…

SOLID-SOURCE DIFFUSED JUNCTION FOR FIN-BASED ELECTRONICS

Granted: January 19, 2017
Application Number: 20170018658
A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of…

INERTIAL MEASUREMENT UNIT FOR ELECTRONIC DEVICES

Granted: January 12, 2017
Application Number: 20170010126
In one example an inertial measurement unit comprises an autocalibration module to compute a covariance matrix from data received from a plurality of sensors, an adaptive weight control module to determine state-based feedback parameters for the gyroscope sensor, accelerometer sensor, and magnetometer sensor, and a sensor characteristic adjustment module to determine a modified covariance matrix based on an input from the adaptive weight control module. Other examples may be described.

ROTATION SENSOR DEVICE

Granted: January 12, 2017
Application Number: 20170010636
embodiments described herein provide for a device that can include a hinge to couple a first housing to a second housing. The hinge can include logic to detect a rotation of the first housing around an axis of the hinge relative to the second housing. The logic may be included in a digital potentiometer integrated within the hinge.

DYNAMIC THREAD SPLITTING

Granted: January 12, 2017
Application Number: 20170010894
Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction…

ACCELERATED LENS DISTORTION CORRECTION WITH NEAR-CONTINUOUS WARPING OPTIMIZATION

Granted: January 12, 2017
Application Number: 20170011493
A digital image processing technique, such as an image warping operation, is stored in a pre-computed lookup table (LUT) prior to image processing. The LUT represents a pixel-to-pixel mapping of pixel coordinates in a source image to pixel coordinates in a destination image. For vectors containing only inlier pixels, a fast remap table is generated based on the original LUT. Each SIMD vector listed in the fast remap is indexed to the coordinates of one of the source pixels that maps to…

SELF-ALIGNED FLOATING GATE IN A VERTICAL MEMORY STRUCTURE

Granted: January 12, 2017
Application Number: 20170011928
A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a…

THROUGH-BODY VIA FORMATION TECHNIQUES

Granted: January 12, 2017
Application Number: 20170011987
Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film…

SEMICONDUCTOR INTERCONNECT STRUCTURES

Granted: January 12, 2017
Application Number: 20170011998
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive…

GERMANIUM-BASED QUANTUM WELL DEVICES

Granted: January 12, 2017
Application Number: 20170012116
A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

TRANSITION METAL DICHALCOGENIDE SEMICONDUCTOR ASSEMBLIES

Granted: January 12, 2017
Application Number: 20170012117
Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a first barrier formed of a first transition metal dichalcogenide (TMD) material, a transistor channel formed of a second TMD material, and a second barrier formed of a third TMD material. The first barrier may be disposed between the transistor channel and the flexible substrate, the…

TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN CONTACTS

Granted: January 12, 2017
Application Number: 20170012124
Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench…

SELECTIVELY REGROWN TOP CONTACT FOR VERTICAL SEMICONDUCTOR DEVICES

Granted: January 12, 2017
Application Number: 20170012126
Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain…

SYSTEMS AND METHODS FOR ENHANCED USER EQUIPMENT ASSISTANCE INFORMATION IN WIRELESS COMMUNICATION SYSTEMS

Granted: January 12, 2017
Application Number: 20170013557
Systems and methods are disclosed for communicating enhanced user equipment (UE) assistance information between nodes in wireless communication systems. The UE achieves power savings and latency requirements more effectively by communicating its preferences, constraints and/or requirements to an evolved Node B (eNodeB) in the form of UE assistance information. The UE assistance information may include, for example, an indication of a preferred set of discontinuous reception (DRX)…

TECHNOLOGIES FOR SELECTIVELY ETCHING OXIDE AND NITRIDE MATERIALS AND PRODUCTS FORMED USING THE SAME

Granted: January 5, 2017
Application Number: 20170004975
Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. By controlling the flow rate of various components of the plasma gas flow, plasmas exhibiting desired etching characteristics may be obtained. Such plasmas may be used in single or multistep etching operations, such as recess etching operations that may be used in the…

METHODS OF FORMING HIGH DENSITY METAL WIRING FOR FINE LINE AND SPACE PACKAGING APPLICATIONS AND STRUCTURES FORMED THEREBY

Granted: January 5, 2017
Application Number: 20170004978
Methods of forming microelectronic device structures are described. Those methods may include forming at least one opening through a build up structure and a photo sensitive material disposed on the build up structure, wherein the build up structure comprises a portion of a package substrate, filling the at least one opening with a metal containing nanopaste, and sintering the metal containing nanopaste to form a bulk property metal structure in the at least one opening.

SELECTIVE ETCHING FOR GATE ALL AROUND ARCHITECTURES

Granted: January 5, 2017
Application Number: 20170005176
The present disclosure relates to a method of etching sacrificial material. The method includes supplying a semiconductor substrate in a reaction chamber, wherein the substrate includes a channel disposed on the substrate and a sacrificial layer disposed on at least a portion of the channel. The method further includes supplying an interhalogen vapor to the reaction chamber, etching at least a portion of the sacrificial layer with the interhalogen vapor and exposing at least a portion of…