Intel Patent Applications

FAST INKING A TOUCH DISPLAY

Granted: April 27, 2017
Application Number: 20170115754
An apparatus for fast inking a touch display is described herein. The system for fast inking a touch display can include receiving touch input and generate touch sensor data. The system can include a graphics processing unit (GPU) including a fast inker and a display pipeline. The GPU can transmit human interface device (HID) data generated from the touch sensor data to a writing application memory and the fast inker. The fast inker can convert the HID data into inking data to be sent to…

TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE

Granted: April 27, 2017
Application Number: 20170115916
Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

UNIVERSAL CONTROLLER TO SUPPORT REMOTE MONITORING OF SYSTEM AND/OR MACHINE HEALTH

Granted: April 27, 2017
Application Number: 20170116137
Systems, apparatuses and methods may provide for determining, at runtime, one or more deviations of a peripheral device from a common interface based on one or more configuration files and translating one or more communications between the peripheral device and an application in accordance with the one or more deviations. In one example, a level of quality of a product dispensed by a system containing the peripheral device may be determined based on the communications. Moreover, a…

SEGMENTED ERASE IN MEMORY

Granted: April 27, 2017
Application Number: 20170117049
Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current…

TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS

Granted: April 27, 2017
Application Number: 20170117378
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate…

PACKET PROCESSING WITH REDUCED LATENCY

Granted: April 27, 2017
Application Number: 20170118143
Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay…

TECHNIQUES FOR VIDEO ANALYTICS OF CAPTURED VIDEO CONTENT

Granted: April 27, 2017
Application Number: 20170118441
Examples are disclosed for video analytics of captured video content. In some examples, information may be received from a host processing system for a camera to capture video content. The camera may be a surveillance camera or a camera located with a display device. Video analytics may be performed on the captured video and the captured video content may be encoded. Data associated with the video analytics may then be sent to the host processing system. In some examples, the data as…

METHOD AND APPARATUS FOR M2M DEVICE SUBSCRIPTION

Granted: April 27, 2017
Application Number: 20170118579
An apparatus may include a processor circuit and a machine type communication (MTC) device setup module operable on the processor circuit to determine when the apparatus is provisioned with a subscription to a local network, and to provide a device setup interface to automatically connect the apparatus to a machine type communication (MTC) subscriber independently of an operator of the local network. Other embodiments are disclosed and claimed.

METHOD AND SYSTEM OF SECURED DIRECT LINK SET-UP (DLS) FOR WIRELESS NETWORKS

Granted: April 27, 2017
Application Number: 20170118633
Method and system of secured direct link set-up (DLS) for wireless networks. In accordance with aspects of the method, techniques are disclosed for setting up computationally secure direct links between stations in a wireless network in a manner that is computationally secure. A direct link comprising a new communication session is set up between first and second stations in a wireless local area network (WLAN) hosted by an access point (AP), the direct link comprising a new…

MESSAGE GENERATING ARRANGEMENT

Granted: April 27, 2017
Application Number: 20170118790
A message generating arrangement determines whether a first communication terminal of a communication system can participate, by means of packet-switching network elements of the communication system, in a communication link in which a second communication terminal of the communication system is participating by means of circuit-switching network elements of the communication system, and generates a message on the basis of the result of the determination.

PULSE DIAGNOSIS

Granted: April 20, 2017
Application Number: 20170105628
In one example a pulse measurement system, comprises at least one sensor positioned to collect pulse information at three separate locations along a body segment, a controller communicatively coupled to the at least one sensor to receive the pulse information from the at least one sensor, and a display coupled to the controller to present at least one characteristic of the pulse information detected at the three separate locations. Other examples may be described.

IMPLIED DIRECTORY STATE UPDATES

Granted: April 20, 2017
Application Number: 20170109285
A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to…

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

Granted: April 20, 2017
Application Number: 20170109286
A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data…

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

Granted: April 20, 2017
Application Number: 20170109287
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER

Granted: April 20, 2017
Application Number: 20170109296
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.

HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS

Granted: April 20, 2017
Application Number: 20170109300
An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a…

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

Granted: April 20, 2017
Application Number: 20170109304
A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

HIGH PERFORMANCE INTERCONNECT

Granted: April 20, 2017
Application Number: 20170109315
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the…

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

Granted: April 20, 2017
Application Number: 20170110422
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another…

VIRTUALIZATION OF NATURAL RADIO ENVIRONMENTS USING FIELD TRACES AND A CHANNEL EMULATOR

Granted: April 20, 2017
Application Number: 20170111126
Natural radio environments are emulated using field traces and a channel emulator to test radio devices. In one example, a test includes a field trace source to replay recorded field traces, a protocol tester to receive the replayed field traces to extract configuration parameters from the replayed field traces, to extract signals from the field traces, to send the signals to a device under test, and to receive signals from the device under test, and a channel emulator coupled to the…