Load balancing optimization for 5G self-organizing networks
Granted: April 16, 2024
Patent Number:
11963041
Various embodiments generally may relate to Load Balancing Optimization (LBO) and Mobility Robustness Optimization (MRO). Some embodiments of this disclosure are directed to the following 5G SON solutions: use cases and requirements for the management of distributed LBO and centralized LBO; procedures for the management of distributed LBO and centralized LBO; and management services and information needed to support the management of distributed LBO and centralized LBO.
Fragment compression for coarse pixel shading
Granted: April 16, 2024
Patent Number:
11961179
One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.
Technologies for fast booting with error-correcting code memory
Granted: April 16, 2024
Patent Number:
11960900
Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The…
Graphics processing unit and central processing unit cooperative variable length data bit packing
Granted: April 16, 2024
Patent Number:
11960887
Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.
Apparatus and method for complex multiplication
Granted: April 16, 2024
Patent Number:
11960884
An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the…
Scalable MCTP infrastructure
Granted: April 16, 2024
Patent Number:
11960439
Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management…
Many-to-many PCIE switch
Granted: April 16, 2024
Patent Number:
11960429
Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many…
Dynamic offline end-to-end packet processing based on traffic class
Granted: April 9, 2024
Patent Number:
11956156
Methods and apparatus for dynamic offline end-to-end packet processing based on traffic class. An end-to-end connection is set up between an application on a client including a processor and host memory and an application on a remote server. An offline packet buffer is allocated in host memory. While the processor and/or a core on with the client application is executed is in a sleep state, the client is operated in an interrupt-less and polling-less mode as applied to a predetermined…
Stackable in-line filter modules for quantum computing
Granted: April 9, 2024
Patent Number:
11957066
Embodiments of the present disclosure describe quantum circuit assemblies that include one or more filter modules integrated in a package with a quantum circuit component having at least one qubit device. Integration may be such that both the quantum circuit component and the filter module(s) are at least partially inside a chamber formed by a radiation shield structure that is configured to attenuate electromagnetic radiation incident on the quantum circuit component and the filter…
Enhanced traffic indications for multi-link wireless communication devices
Granted: April 9, 2024
Patent Number:
11956663
This disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (MLDs). A device may generate a first traffic indication map (TIM) with a first bitmap including a first indication that traffic is to be sent by a first access point (AP) device of the MLD to a first non-AP device of a second MLD using a first communication link. The device may generate a second TIM with a second bitmap including a second indication that no traffic is to be sent…
Lined photobucket structure for back end of line (BEOL) interconnect formation
Granted: April 9, 2024
Patent Number:
11953826
Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to…
Methods and apparatus for machine learning-guided compiler optimizations for register-based hardware architectures
Granted: April 9, 2024
Patent Number:
11954466
Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning…
Apparatuses, methods, computer programs, and data carriers for indicating and detecting atomic operations
Granted: April 9, 2024
Patent Number:
11954465
An apparatus comprising at least one interface configured to read one or more high-level code instructions; and at least one processor configured to read the one or more high-level code instructions using the interface, determine atomic operations in the high-level code instructions, and translate the one or more high-level code instructions into assembly code instructions, wherein atomic operations are indicated in the assembly code instructions based on the atomic operations in the…
Dual bayesian encoding-decoding technique for text to code transformations
Granted: April 9, 2024
Patent Number:
11954462
Methods, apparatus, and software for implementing dual Bayesian encoding-decoding for text-to-code transformations. In one aspect, a multi-model probabilistic source code model employing dual Bayesian encoder-decoder models is used to convert natural language (NL) inputs (aka requests) into source code. An NL input is processed to generate a Probabilistic Distribution (PD) of Source code (SC) tokens in an SC token sequence and a PD of Abstract Syntax Tree (AST) tokens in an AST token…
Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links
Granted: April 9, 2024
Patent Number:
11954360
Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being…
Apparatus, method, and system for collecting cold pages
Granted: April 9, 2024
Patent Number:
11954356
Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are…
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
Granted: April 9, 2024
Patent Number:
11954063
Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an…
Circuitry and methods for spatially unique and location independent persistent memory encryption
Granted: April 9, 2024
Patent Number:
11954047
Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component…
Object and cacheline granularity cryptographic memory integrity
Granted: April 9, 2024
Patent Number:
11954045
Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline…
System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis
Granted: April 9, 2024
Patent Number:
11953962
In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
