Localized high density substrate routing
Granted: May 14, 2024
Patent Number:
11984396
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically…
Fabrication of stackable embedded eDRAM using a binary alloy based on antimony
Granted: May 14, 2024
Patent Number:
11985909
Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface…
Mode-1 downlink control information transmission-reception for configured sidelink scheduling in NR V2X
Granted: May 14, 2024
Patent Number:
11985670
Various embodiments of the present disclosure may be used to determine how activation downlink control information (DCI), release DCI, and dynamic retransmission DCI are distinguished for DCI formats 3_0/3_1 for Mode-1 sidelink resource allocation. Furthermore, in case of asynchronous downlink (DL) and sidelink (SL) carriers, embodiments of the present disclosure may be used to determine how a user equipment (UE) determines transmission slots with respect to system frame number (SFN) or…
Distributed minimum mean-square error interference rejection combining (MMSE-IRC) processing for radio access networks
Granted: May 14, 2024
Patent Number:
11985011
Various embodiments herein provide techniques for minimum mean-square error interference rejection combining (MMSE-IRC) processing of a received signal, distributed between a baseband unit (BBU) and a remote radio unit (RRU). The RRU may perform a first phase of processing based on an extended channel that includes a channel of one or more user equipments (UEs) served by the RRU and interference samples that correspond to other cells or additive noise. The first phase may include scaling…
Prioritization of services for control and data transmission for new radio systems
Granted: May 14, 2024
Patent Number:
11984987
Methods, systems, and storage media are described for the prioritization of services for control and data transmission for new radio (NR) systems. In particular, some embodiments may be directed to the prioritization of hybrid automatic repeat request-acknowledgment (HARQ-ACK) transmissions. Other embodiments may be described and/or claimed.
Memory structure for self-erasing secret storage
Granted: May 14, 2024
Patent Number:
11984512
In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month,…
Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer
Granted: May 14, 2024
Patent Number:
11984506
Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric…
Non-planar transistor arrangements with asymmetric gate enclosures
Granted: May 14, 2024
Patent Number:
11984487
Disclosed herein are non-planar transistor (e.g., nanoribbon) arrangements having asymmetric gate enclosures on at least one side. An example transistor arrangement includes a channel material shaped as a nanoribbon, and a gate stack wrapping around at least a portion of a first face of the nanoribbon, a sidewall, and a portion of a second face of the nanoribbon. Portions of the gate stack provided over the first and second faces of the nanoribbon extend in a direction parallel to the…
Microelectronic assemblies
Granted: May 14, 2024
Patent Number:
11984439
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is…
Hyperchip
Granted: May 14, 2024
Patent Number:
11984430
Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second…
Vertical inductor for WLCSP
Granted: May 14, 2024
Patent Number:
11984246
Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be…
Unified memory compression mechanism
Granted: May 14, 2024
Patent Number:
11983791
An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.
System, apparatus and method for persistently handling memory requests in a system
Granted: May 14, 2024
Patent Number:
11983437
In one embodiment, an apparatus includes: a first queue to store requests that are guaranteed to be delivered to a persistent memory; a second queue to store requests that are not guaranteed to be delivered to the persistent memory; a control circuit to receive the requests and to direct the requests to the first queue or the second queue; and an egress circuit coupled to the first queue to deliver the requests stored in the first queue to the persistent memory even when a power failure…
Ballooning for multi-tiered pooled memory
Granted: May 14, 2024
Patent Number:
11983408
An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other…
Partitioned platform security mechanism
Granted: May 14, 2024
Patent Number:
11983260
A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
Glass core patch with in situ fabricated fan-out layer to enable die tiling applications
Granted: May 7, 2024
Patent Number:
11978685
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first…
Die with embedded communication cavity
Granted: May 7, 2024
Patent Number:
11978948
Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.
Recessed thin-channel thin-film transistor
Granted: May 7, 2024
Patent Number:
11978804
A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the…
Gate-all-around integrated circuit structures having germanium nanowire channel structures
Granted: May 7, 2024
Patent Number:
11978784
Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor…
Semiconductor device stack-up with bulk substrate material to mitigate hot spots
Granted: May 7, 2024
Patent Number:
11978689
Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a…
