High Performance Semi-Rigid Wall Protection System
Granted: September 27, 2018
Application Number:
20180272677
A wall protection system includes a backing layer, an intermediate layer, and a top layer. The intermediate layer is secured to the backing layer and includes a flexible polyvinyl chloride (PVC). The top layer is secured to the intermediate layer and includes a rigid PVC. In various aspects, the PVC of the intermediate layer is rigid relative to the PVC of the top layer. In certain aspects, a method of installing a wall protection system includes thermally bonding a rigid PVC layer to a…
DATA RATE AND PVT ADAPTATION WITH PROGRAMMABLE BIAS CONTROL IN A SERDES RECEIVER
Granted: May 19, 2016
Application Number:
20160142233
Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through…
Slice-Based Random Access Buffer for Data Interleaving
Granted: February 4, 2016
Application Number:
20160034393
The disclosure is directed to a system and method for interleaving data utilizing a random access buffer that includes a plurality of independently accessible memory slots. The random access buffer is configured to store slices of incoming data sectors in free memory slots, where a free memory slot is identified by a status flag associated with a logical address of the free memory slot. Meanwhile, a label buffer is configured to store labels associated with the slices of the incoming…
HOST-BASED DEVICE DRIVERS FOR ENHANCING OPERATIONS IN REDUNDANT ARRAY OF INDEPENDENT DISKS SYSTEMS
Granted: February 4, 2016
Application Number:
20160034186
Methods and structure for host-side device drivers for Redundant Array of Independent Disks (RAID) systems. One system includes a processor and memory of a host, which implement a device driver. The device driver receives an Input/Output (I/O) request from an Operating System (OS) of the host, translates Logical Block Addresses (LBAs) from the received request into physical addresses at multiple storage devices, generates child I/O requests directed to the physical addresses based on the…
Systems and Methods for Rank Independent Cyclic Data Encoding
Granted: January 28, 2016
Application Number:
20160028419
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.
Systems and Methods for Self Test Circuit Security
Granted: January 21, 2016
Application Number:
20160020158
The present inventions are related to systems and methods for circuit implementation, and more particularly to systems and methods for securing data in a circuit.
MEMORY BANKS WITH SHARED INPUT/OUTPUT CIRCUITRY
Granted: December 3, 2015
Application Number:
20150348594
A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The…
PLL Scan Method for HDTV Products
Granted: December 3, 2015
Application Number:
20150350721
A system and method for improved channel scanning in an HDTV device queries a database with location data input by the user, receiving an ordered list of potential channels associated with the selected location. The system may scan only those potential channels on the ordered list, storing successfully decoded channels in memory. The system may further divide the ordered list into groups based on the relative signal strength of potential channels. If a potential channel of the lowest…
SELECTING FLOATING TAP POSITIONS IN A FLOATING TAP EQUALIZER
Granted: December 3, 2015
Application Number:
20150349988
In one embodiment, an apparatus has an equalizer, a tap position locator, and a tap weight updater. The equalizer has a plurality of floating taps. The tap position locator generates metrics for a set of possible tap positions of the equalizer. Each possible tap position corresponds to a different tap weight, and the metrics are generated without updating the tap weights for all of the possible tap positions in the set. Further, the tap position locator selects a subset of possible tap…
SCALABLE MAPPING WITH INTEGRATED SUMMING OF SAMPLES FOR MULTIPLE STREAMS IN A RADIO INTERFACE FRAME
Granted: December 3, 2015
Application Number:
20150349811
An apparatus includes a first circuit, a second circuit, and a third circuit. The first circuit may be configured to buffer a plurality of antenna carrier sample streams. The second circuit is coupled to the first circuit and may be configured to generate message data through pipelined processing and mapping of the antenna carrier samples. The third circuit is coupled to the second circuit and may be configured to generate a master frame in response to the processed and mapped message…
Storage Controller and Method for Managing Metadata in a Cache Store
Granted: December 3, 2015
Application Number:
20150347310
A cache controller coupled to a cache store supported by a solid-state memory element uses a metadata update process that reduces write amplification caused by writing both cache data and metadata to the solid-state memory element. The cache controller partitions the solid-state memory element to include a metadata portion, a host data or cache portion and a log portion. Host write requests that include “hot” data are processed and recorded by the cache controller. The cache…
Forced Map Entry Flush to Prevent Return of Old Data
Granted: December 3, 2015
Application Number:
20150347289
A data storage device flushes newly written data in response to certain events such that, when the device has acknowledged newly written data, the device cannot return old data of the referenced logical block address to the host in any case. If the data of the logical block address has been corrupted, the device returns an uncorrectable error, not old data. A “force map entry flush” flushes modified map entries to NAND when an upper page is programmed. After a power failure and…
DWELL TIMERS FOR SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE DEVICES
Granted: December 3, 2015
Application Number:
20150346762
Methods and structure for dwell timers in Serial Attached Small Computer System Interface (SAS) devices. An exemplary system includes a SAS end device. The SAS end device includes a physical link (PHY) operable to receive an OPEN Address Frame (OAF) from a coupled SAS device. The SAS end device also includes a controller. The controller is able to determine that the end device is presently unable to service a connection, and to wait a period of time for a dwell timer to expire. The…
FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION
Granted: November 26, 2015
Application Number:
20150339189
An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to…
VOLTAGE COMPARATOR
Granted: November 19, 2015
Application Number:
20150333745
A voltage comparator for comparing reference voltage applied to a first input node to an input voltage applied to a second input node. A first pair of transistors have output terminals coupled in series between the first input node and common node, and gate terminals connected together. A second pair of transistors, having both gate terminals of the pair connected to the gate terminals of the first pair of transistors, have output terminals coupled in series between a second input…
MEMORY CELL HAVING BUILT-IN READ AND WRITE ASSIST
Granted: November 19, 2015
Application Number:
20150332755
A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching…
SIDEBAND LOGIC FOR MONITORING PCIe HEADERS
Granted: November 19, 2015
Application Number:
20150331773
Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets.
COORDINATION TECHNIQUES FOR REDUNDANT ARRAY OF INDEPENDENT DISKS STORAGE CONTROLLERS
Granted: November 19, 2015
Application Number:
20150331765
Methods and structure for coordinating between Redundant Array of Independent Disks (RAID) storage controllers are provided. An exemplary system includes a RAID controller. The RAID controller includes a Peripheral Component Interconnect Express (PCIe) interface, a Serial Attached Small Computer System Interface (SAS) port operable to communicate with another RAID controller, and a command unit. The command unit is able to direct the interface to contact another PCIe interface at the…
METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER
Granted: November 19, 2015
Application Number:
20150331748
An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error…
SYSTEM FOR REDUCING TEST TIME USING EMBEDDED TEST COMPRESSION CYCLE BALANCING
Granted: November 12, 2015
Application Number:
20150323595
An apparatus for reducing test time is disclosed. The apparatus includes a processor operable to execute one or more modules to cause the processor to receive operational parameters associated with a first scan chain grouping circuitry and a second scan chain grouping circuitry of an integrated circuit design. The operational parameters include a number of initialization cycles of a first test signal selected for the first scan chain grouping circuitry, a number of initialization cycles…
