SYSTEMS AND METHODS FOR VOLTAGE LEVEL SHIFTING IN A DEVICE
Granted: September 17, 2015
Application Number:
20150263732
Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage…
Method for Fabricating Equal Height Metal Pillars of Different Diameters
Granted: September 17, 2015
Application Number:
20150262950
A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first…
Method for Fabricating Equal Height Metal Pillars of Different Diameters
Granted: September 17, 2015
Application Number:
20150262949
A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and first openings in the photoresist are formed. Metal layers are formed by electroplating metal into the first openings for a first time period. Then the photoresist is patterned to form second openings having a smaller diameter than the first openings. Narrow…
METHOD AND SYSTEM FOR REDUCING MEMORY TEST TIME UTILIZING A BUILT-IN SELF-TEST ARCHITECTURE
Granted: September 17, 2015
Application Number:
20150262710
Methods and systems for reducing memory test time utilizing a serial per march element communicating architecture. A small number of slow speed signals can be configured between a BIST wrapper and a BIST controller to transfer information in accordance with a BIST sequence that includes a number of march elements. An information transfer protocol can be implemented between the BIST wrapper and the BIST controller to transfer Information with respect to each march element that includes a…
LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY
Granted: September 17, 2015
Application Number:
20150262667
An apparatus includes a hit bitline driver circuit and an equalization control circuit. The hit bitline driver circuit may be configured to drive a pair of hit bitlines responsive to a search bit. The equalization control circuit may be configured to transfer charge from one hit bitline of the pair to the other hit bitline of the pair in response to the search bit changing state.
Systems and Methods for Head Position Estimation
Granted: September 17, 2015
Application Number:
20150262598
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.
Systems and Methods for Distortion Characterization
Granted: September 17, 2015
Application Number:
20150262592
Systems, methods, devices and circuits for data amplification, and more particularly systems and methods for characterizing distortion introduced during data amplification. In some cases, an amplifier modeling circuit is discussed that receives a preamplifier status input from a preamplifier circuit; applies a vector fitting algorithm to the preamplifier status to yield a pole value; determines that the pole value is greater than unity; and replaces the pole value with an inverse of the…
DATA TRANSFORMATIONS TO IMPROVE ROM YIELD AND PROGRAMMING TIME
Granted: September 17, 2015
Application Number:
20150261636
Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can…
Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE)
Granted: September 10, 2015
Application Number:
20150256363
An N-way parallel, unrolled decision feedback equalizer for a SerDes receiver can convert between four-tap PAM-2 and two-tap PAM-4 mode, maximizing hardware through the use of mode control multiplexers. Each of N interleaved parallel branches includes an ISI correction stage for generating a partial result approximating intersymbol interference and comparing the partial result to a threshold, a carry look-ahead stage for generating a second partial result based in part on previously…
GROUP DELAY BASED BACK CHANNEL POST CURSOR ADAPTATION
Granted: September 10, 2015
Application Number:
20150256364
Described embodiments provide for de-coupling between adaptation of decision feedback equalizer (DFE) filter taps and transmitter (TX) post cursor filtering in group delay (GD)-based adaptation. Consequently, an excessive build-up of transmitter post cursor effects and its excessive equalization cancellation by the DFE may be substantially reduced or eliminated. By breaking this coupling, a transmitter does not over equalize a signal, the DFE does not attempt to “undo” the over…
SOFT DECODING OF POLAR CODES
Granted: September 10, 2015
Application Number:
20150256196
An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.
BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES
Granted: September 10, 2015
Application Number:
20150255148
SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that…
Online Iteration Resource Allocation for Large Sector Format Drive
Granted: September 10, 2015
Application Number:
20150255113
Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc…
Non-Decision Directed Magnetoresistive Asymetry Estimation
Granted: September 10, 2015
Application Number:
20150255109
Systems and methods for magnetoresistive asymmetry estimation may include, but are not limited to, operations for: receiving a magnetic read head transducer output; computing a mean value of the magnetic read head transducer output; computing a median value of the magnetic read head transducer output; and applying a correction coefficient to a magnetic read head detector input according to at least the mean value of the magnetic read head transducer output and the median value of the…
TRACK MISREGISTRATION SENSITIVE INITIALIZATION OF JOINT EQUALIZER
Granted: September 10, 2015
Application Number:
20150255101
A method of mitigating an effect of track misregistration on read performance in a system comprising an array-reader includes determining an estimated off-track condition, selecting translation coefficients based on the estimated off-track condition, determining updated equalizer coefficients by applying the translation coefficients to native equalizer coefficients, and applying the updated equalizer coefficients to signals received from the array-reader to output a read signal.
SERDES PVT DETECTION AND CLOSED LOOP ADAPTATION
Granted: September 3, 2015
Application Number:
20150249555
In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA…
STORAGE WORKLOAD HINTING
Granted: August 27, 2015
Application Number:
20150242133
Methods and structure for reconfiguring storage systems are provided. One exemplary embodiment is a storage controller. The storage controller includes a memory that stores multiple profiles that are each designated for a different type of Input/Output processing workload from a host, and each include settings for managing communications with coupled storage devices. Each type of workload is characterized by a pattern of Input/Output requests from the host. The storage controller also…
Reading Data from Hard Disks Having Reduced Preambles
Granted: August 27, 2015
Application Number:
20150243321
An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is…
Systems and Methods for Synchronization Hand Shaking in a Storage Device
Granted: August 27, 2015
Application Number:
20150243311
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection…
Systems and Methods for Multi-Head Separation Determination
Granted: August 27, 2015
Application Number:
20150243310
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.
