LSI Patent Grants

Method and system for dynamic storage tiering using allocate-on-write snapshots

Granted: October 27, 2015
Patent Number: 9170756
System and method for dynamic storage tiering are disclosed. A storage hot-spot in a first storage pool is detected. A first point-in-time copy of a virtual volume including the storage hot-spot is created in a second storage pool according to the detecting. Write requests directed to the virtual volume are redirected to the second storage pool. When decreased I/O activity directed to the storage hot-spot in the second storage pool is detected, the point-in-time copy in the second…

Cross-talk measurement in array reader magnetic recording system

Granted: October 6, 2015
Patent Number: 9153249
An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second…

Non-binary layered low density parity check decoder

Granted: September 8, 2015
Patent Number: 9130590
A non-binary layered low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on normalized check node to variable node messages and on normalized decoder inputs, and to output normalized decoded values, and a check node processor operable to generate the check node to variable node messages based on normalized variable node to check node messages.

Systems and methods for modified quality based priority scheduling during iterative data processing

Granted: July 28, 2015
Patent Number: 9092368
Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As one example, a data processing system is disclosed that includes a data detector circuit, a data decoder circuit, a memory circuit, and a scheduling circuit. The scheduling circuit is operable to select one of a first data set and the second data set as a detector input for processing by the data detector…

Flaw scan circuit for repeatable run out (RRO) data

Granted: July 28, 2015
Patent Number: 9093096
Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a…

Skew-tolerant reader set selection in array-reader based magnetic recording

Granted: July 28, 2015
Patent Number: 9093119
A method for enhancing read performance in an ARMR system includes: obtaining CTS information for a plurality of readers in a multi-reader head of the ARMR system, the CTS information defining a relationship between skew angle and CTS between respective combinations of subsets of the readers; determining, as a function of the CTS information, a given one of the combinations of subsets of the readers which provides enhanced read performance among a total number of combinations of subsets…

Systems and methods for variable sector count spreading and de-spreading

Granted: July 28, 2015
Patent Number: 9094046
Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.

Systems and methods for rapid erasure retry decoding

Granted: July 7, 2015
Patent Number: 9076492
Data processing systems, circuits and methods are disclosed. As one example, a data processing system is disclosed that includes: a buffer circuit, a data processing circuit, and an erasure window set circuit. The buffer circuit is operable to store a data set as a buffered data set, and the data processing circuit is operable to repeatedly apply a data processing algorithm to the buffered data set. The erasure window set circuit is operable to define a location of the erasure window in…

Systems and methods for timing control in a data processing system

Granted: June 23, 2015
Patent Number: 9064539
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for synchronizing operations in a data storage system.

Systems and methods for multi-dimensional data processor operational marginalization

Granted: June 16, 2015
Patent Number: 9058115
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

Systems and methods for gate aware iterative data processing

Granted: June 16, 2015
Patent Number: 9058842
The present inventions are related to systems and methods for iterative data processing scheduling. In one case a data processing system is disclosed that includes a data detector circuit and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The data decoder circuit is operable to repeatedly apply a data decoding algorithm to the detected output to yield a decoded output over a number of passes,…

Ratio-adjustable sync mark detection system

Granted: June 9, 2015
Patent Number: 9053217
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.

Pipelined vectoring-mode CORDIC

Granted: June 2, 2015
Patent Number: 9047148
Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector…

Systems and methods for multi-level encoding and decoding

Granted: June 2, 2015
Patent Number: 9047882
A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level encoder operable to encode the data set at a plurality of different code rates before it is written to the storage medium, and a multi-level decoder operable to decode the data set retrieved from the storage medium and to apply decoded values encoded at a lower code rate…

Memory device having control circuitry for write tracking using feedback-based controller

Granted: June 2, 2015
Patent Number: 9047936
A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory…

Shift register-based layered low density parity check decoder

Granted: June 2, 2015
Patent Number: 9048867
An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate…

Low density parity check decoder with flexible saturation

Granted: June 2, 2015
Patent Number: 9048870
Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values.

Systems and methods for multi-stage encoding of concatenated low density parity check codes

Granted: June 2, 2015
Patent Number: 9048873
A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

Min-sum based hybrid non-binary low density parity check decoder

Granted: June 2, 2015
Patent Number: 9048874
An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and…

Systems and methods for variable redundancy data protection

Granted: May 26, 2015
Patent Number: 9043684
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.