Chip-Scale Package Conversion Technique for Dies
Granted: July 15, 2010
Application Number:
20100180249
A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding…
BANDGAP-REFERENCED THERMAL SENSOR
Granted: June 3, 2010
Application Number:
20100134180
A thermal sensor for an integrated circuit including a bandgap reference circuit. The thermal sensor includes a comparator that compares a temperature dependent voltage generated by the bandgap reference circuit to a temperature independent voltage, where both temperatures are referenced to the bandgap reference voltage generated by the bandgap reference circuit. The thermal sensor generates a digital output control signal based on a predetermined relationship between the temperature…
Line Driver With Tuned On-Chip Termination
Granted: March 18, 2010
Application Number:
20100066405
A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed…
SYSTEM FOR VERTICAL DMOS WITH SLOTS
Granted: March 18, 2010
Application Number:
20100065906
A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an…
Dual Input LDO Regulator With Controlled Transition Between Power Supplies
Granted: March 11, 2010
Application Number:
20100060078
A Dual Input, Single Output Low Dropout Regulator (LDO) includes two linear regulator circuits and control circuitry that produce an overlap period during change-over between a regulated supply voltage and an unregulated supply voltage wherein both supply voltages are coupled to the LDO output pin. The unregulated supply voltage is supplied, e.g., by a battery, and the regulated supply voltage is supplied from a switching-type DC-DC converter. First and second output devices are…
SLEW RATE CONTROLLED LEVEL SHIFTER WITH REDUCED QUIESCENT CURRENT
Granted: March 4, 2010
Application Number:
20100052735
A level shifter circuit includes two parallel current paths respectively controlled by switch transistors, a Wilson current mirror circuit, and a slew rate control circuit to selectively couple an output node either to a high (first) voltage source or to a ground (second voltage) source in response to differential input control signals signal. When the output node reaches a stable (high or low) voltage level, the low voltage on one of the current paths turns off a Wilson current mirror…
Tester for RF Devices
Granted: March 4, 2010
Application Number:
20100052708
For testing an RF device, such as an RF receiver/decoder chip that receives an RF signal via an antenna terminal and outputs a digital code at an output terminal, an inexpensive non-RF programmable tester is used. The programmable tester is a commercially available tester that need only generate and receive non-RF digital and analog signals. The RF signals needed for the testing of the RF device are totally supplied by RF generators on a single printed circuit board, external to the…
MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness
Granted: February 11, 2010
Application Number:
20100032753
A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self-aligned to a first spacer, a second diffusion region formed a first distance away from the edge of a second spacer, a first contact opening and metallization formed above the first diffusion region, and a second contact…
True Ring Networks Using Tag VLAN Filtering
Granted: January 28, 2010
Application Number:
20100020809
A method in a network device configured in a true ring network where the network device has a first port and a second port connected to the true ring network and a third port connected to a processor including: connecting the network device to transmit data packets in a single direction around the true ring network including an ingress port and an egress port; enabling ingress tag VLAN filtering on the ingress port only; configuring a VLAN table in the network device to terminate an…
True Ring Networks With Gateway Connections Using MAC Source Address Filtering
Granted: January 28, 2010
Application Number:
20100020798
A method in a network device implements source address filtering, including gateway address filtering, to enable network devices to be configured in a true Ethernet ring network. By implementing source address filtering or source address filtering with gateway address filtering, a true ring network can be formed using Ethernet protocols where all the links between the network devices in the ring are active paths while avoiding data packets being switched endlessly around the ring. In one…
Current Sensing In a Buck-Boost Switching Regulator Using Integrally Embedded PMOS Devices
Granted: January 14, 2010
Application Number:
20100007316
A current sense device for a power transistor is described. The power transistor is formed in a cellular structure including a cellular array of transistor cells. The current sense device includes multiple transistor cells in the cellular array of transistor cells of the power transistor being used as sense transistor cells. The sense transistor cells are evenly distributed throughout the cellular array where the source terminal of each sense transistor cell is electrically connected to…
Ethernet Controller Using Same Host Bus Timing for All Data Object Access
Granted: January 14, 2010
Application Number:
20100011140
An Ethernet controller has a host interface for coupling to a host processor and a physical layer transceiver for coupling to a data network and includes multiple data objects having different access times where the data objects communicate with the host interface over an internal data bus. The Ethernet controller includes a data object interface module coupled between the host interface and the internal data bus where the data object interface module has a first access time for handling…
Ethernet Controller Implementing a Performance and Responsiveness Driven Interrupt Scheme
Granted: January 14, 2010
Application Number:
20100008378
A method of generating frame receive interrupts in an Ethernet controller including receiving incoming data frames and storing data frames into a receive queue, monitoring the number of received data frames, and when the number of received data frames exceeds a first threshold, generating a frame receive interrupt. In another embodiment, the method further includes monitoring the amount of received data stored in the receive queue and generating a frame receive interrupt when the first…
SYSTEM AND METHOD FOR DETERMINING IN-LINE INTERFACIAL OXIDE CONTACT RESISTANCE
Granted: January 14, 2010
Application Number:
20100007363
The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for measuring in-line contact resistance in relation to oxide formations. The present invention, in one or more implementations, include an in-line method of determining contact resistance across a semiconductor wafer and determining the contact resistance value and the number of monolayers of the wafer.
Method Of Operating Radio Receiver Implemented In A Single CMOS Integrated Circuit
Granted: December 10, 2009
Application Number:
20090305658
A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in…
METHOD AND SYSTEM FOR VERTICAL DMOS WITH SLOTS
Granted: December 10, 2009
Application Number:
20090302378
A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted…
METHOD OF IMPLEMENTING POWER-ON-RESET IN POWER SWITCHES
Granted: November 19, 2009
Application Number:
20090284289
A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power…
Adaptive Compensation Scheme for LC Circuits In Feedback Loops
Granted: November 19, 2009
Application Number:
20090284235
A method for providing adaptive compensation for an electrical circuit where the electrical circuit includes an inductor-capacitor network connected in a feedback loop being compensated by a first compensation capacitance value and a second compensation capacitance value defining the frequency locations of two compensation zeros includes: measuring the inductance value of the inductor; when the inductance value is greater than a first threshold value, increasing the first and second…
NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness
Granted: November 19, 2009
Application Number:
20090283843
A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and…
Boost LED Driver Not Using Output Capacitor and Blocking Diode
Granted: November 5, 2009
Application Number:
20090273290
An LED driver is disclosed that boosts an input voltage to drive any number of LEDs in series. The driver includes a switch-mode current regulator that supplies regulated current pulses to the LEDs. No high voltage output capacitor is used to smooth the current pulses, so the LEDs are turned on any off at the switching frequency. Also, no blocking diode between the switching transistor and the LEDs is used. The cathode of the “bottom” LED in the string is connected to ground via a…
