Microsoft Patent Applications

VOLTAGE BOOST CIRCUIT FOR A STYLUS PEN

Granted: March 23, 2017
Application Number: 20170083119
A stylus pen is disclosed that can be used as an input device to a digitizer associated with a computer screen on a computing device, such as a computer, mobile device, tablet, etc. The stylus pen can include a voltage boost circuit that generates a stylus output signal on an antenna output. The voltage boost circuit has a charging portion and a discharging portion. Both portions have transistors that are activated and deactivated through pulsed control signals. However, a pulse duration…

FOCUSED ATTENTION IN DOCUMENTS AND COMMUNICATIONS

Granted: March 23, 2017
Application Number: 20170083211
Focused attention elements are provided as a mechanism to explicitly call a user's attention to a specific part of a communication or a document. The fact that a user was mentioned in a conversation or a collaborated document may be used as a signal the conversation or a document section is more relevant to them. If a user whose attention is drawn through a focused attention element is not among the recipient list of the communication or collaborator list for the document, they may be…

NESTED COMMUNICATION OPERATOR

Granted: March 23, 2017
Application Number: 20170083301
A high level programming language provides a nested communication operator that partitions a computational space. An indexable type with a rank and element type defines the computational space. The nested communication operator partitions a specified dimension of an index indexable type into segments specified by a segmentation vector and returns an output indexable type that represents the segments. By doing so, the nested communication operator allows data parallel algorithms to…

GENERATION AND USE OF MEMORY ACCESS INSTRUCTION ORDER ENCODINGS

Granted: March 23, 2017
Application Number: 20170083324
Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on…

Dynamic generation of null instructions

Granted: March 23, 2017
Application Number: 20170083325
Apparatus and methods are disclosed for dynamic nullification of memory access instructions, such as memory store instructions. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores. One of the cores can include an execution unit configured to execute memory access instructions comprising a plurality of memory load and/or memory store instructions contained in an instruction block. The core can also include a hardware…

REGISTER READ/WRITE ORDERING

Granted: March 23, 2017
Application Number: 20170083326
Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous…

IMPLICIT PROGRAM ORDER

Granted: March 23, 2017
Application Number: 20170083327
Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions…

STORE NULLIFICATION IN THE TARGET FIELD

Granted: March 23, 2017
Application Number: 20170083328
Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for…

WRITE NULLIFICATION

Granted: March 23, 2017
Application Number: 20170083329
Apparatus and methods are disclosed for nullifying one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain a register identification of at least…

MULTI-NULLIFICATION

Granted: March 23, 2017
Application Number: 20170083330
Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an…

MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS

Granted: March 23, 2017
Application Number: 20170083331
Apparatus and methods are disclosed for performing memory operations instructions in a block-based processor architecture. In certain examples of the disclosed technology, a block-based processor core coupled to memory includes a control unit configured to issue one or more memory operations encoded in an instruction block allocated to the core and to commit the core when execution of the instruction block is complete, a memory store queue configured to cache one or more operands for the…

BLOCK-BASED PROCESSOR CORE TOPOLOGY REGISTER

Granted: March 23, 2017
Application Number: 20170083334
Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the…

INTELLIGENT TABULAR BIG DATA PRESENTATION IN SEARCH ENVIRONMENT BASED ON PRIOR HUMAN INPUT CONFIGURATION

Granted: March 23, 2017
Application Number: 20170083526
An intelligent tabular big data presentation in search environment based on prior human input configuration is provided. In some examples, a server may execute a search service that may receive a request from a party associated with the data to modify a presentation of a subset of the data and may present configuration options to the requesting party. The configuration options may include a selection of the subset of the data and parameters associated with the presentation of the subset…

CONTROLLABLE MARKING

Granted: March 23, 2017
Application Number: 20170083806
The description relates to controllable device marking. One example can be manifest as a device that has a housing and a marking apparatus integrated into the housing. The marking apparatus can include a display and a disablement mechanism. While the disablement mechanism is in a first state the display is controllable to allow content presented on the display to be defined and when the disablement mechanism is transitioned to a second state the content is persisted and unchangeable on…

TECHNIQUES TO MANAGE REMOTE EVENTS

Granted: March 23, 2017
Application Number: 20170083866
Techniques to manage remote events are described. An apparatus may comprise a processor circuit and a remote event application arranged for execution by the processor circuit. The remote event application may be operative to manage remote event notifications for a publisher entity and a subscriber entity. The remote event application may comprise, among other elements, an event monitor component operative to receive an external event notification message with a publisher entity event for…

INFORMATION MANAGEMENT SYSTEMS WITH TIME ZONE INFORMATION, INCLUDING EVENT SCHEDULING PROCESSES

Granted: March 23, 2017
Application Number: 20170083875
Information management systems with time zone information, including event scheduling processes are disclosed. One aspect of the invention is directed toward a computer-implemented scheduling method that can include identifying a difference between a participant time zone and a user time zone, reviewing availability information for the participant and/or one or more selected time preference periods for the participant, and selecting a time range for an event. The method can further…

Device Theft Protection Associating A Device Identifier And A User Identifier

Granted: March 23, 2017
Application Number: 20170085386
When theft protection of a computing device is initiated, credentials of the user are provided to one or more services that verify the credentials and generate a recovery key. A data value is generated based on the recovery key and an identifier of the computing device (e.g., by applying a cryptographic hash function to the recovery key and the computing device identifier), and the data value is provided to the computing device, which stores the data value at the computing device. When a…

UNIVERSAL MOBILE DEVICE MESSAGING

Granted: March 23, 2017
Application Number: 20170085521
A unified messaging system allows the receipt and sending of different messages across devices is established by creating relationships that leverage the capabilities of different devices. A message server establishes a relationship with a mobile device. Through the relationship, the message server can use the mobile device to send different types of messages that the server computer cannot transmit. A relationship between a client and a server extends this capability to the client.…

Shared Scene Mesh Data Synchronization

Granted: March 23, 2017
Application Number: 20170085835
A user device within a communication architecture, the user device comprising: an image capture device configured to determine image data and intrinsic/extrinsic capture device data for the creation of a video channel defining a shared scene; a surface reconstruction entity configured to determine surface reconstruction data associated with the image data from the image capture device; a video channel configured to encode and packetize the image data and intrinsic/extrinsic capture…

Wireless Connectivity Using White Spaces

Granted: March 23, 2017
Application Number: 20170086078
Techniques for wireless connectivity using white spaces (e.g., television (TV) white spaces) are described. In at least some embodiments, movement of a device operating as a white space access point is monitored by local sensors within the device. Movement data that is gathered by the local sensors is used to determine an upper bound of distance traveled. When the upper bound reaches a threshold distance, various actions can be performed relating to the data transmission, such as to…