Nvidia Patent Applications

MANAGING DEFERRED CONTEXTS IN A CACHE TILING ARCHITECTURE

Granted: July 20, 2017
Application Number: 20170206623
A method for managing bind-render-target commands in a tile-based architecture. The method includes receiving a requested set of bound render targets and a draw command. The method also includes, upon receiving the draw command, determining whether a current set of bound render targets includes each of the render targets identified in the requested set. The method further includes, if the current set does not include each render target identified in the requested set, then issuing a…

MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM

Granted: June 29, 2017
Application Number: 20170185526
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the…

Hybrid Parallel Decoder Techniques

Granted: May 25, 2017
Application Number: 20170150181
Decoder techniques in accordance with embodiment of the present technology include partially decoding a compressed file on a serial based processing unit to find offsets of each of a plurality of entropy data blocks. The compressed file and offset for each of the plurality of entropy encoded data blocks are transferred to a parallel based processing unit. Thereafter, the compressed file is at least partially decoded on the parallel based processing unit using the offset for each of the…

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS

Granted: October 13, 2016
Application Number: 20160300319
A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The…

LOW COMPLEXITY ADAPTIVE TEMPORAL FILTERING FOR MOBILE CAPTURES

Granted: September 29, 2016
Application Number: 20160284060
A method of noise filter parameter adaptation, the method comprising receiving a current video frame comprising a plurality of pixels. A table lookup is performed, using current statistical values associated with the current video frame. Noise filter parameters are adapted, based on current lighting conditions as determined from the performed table lookup. The current lighting conditions correspond to the current statistical values. The current video frame is noise filtered as defined by…

Image Scaling Techniques

Granted: March 3, 2016
Application Number: 20160063676
Image scaling techniques, in accordance with embodiments of the present technology, include directionally interpolating blocks of pixel data of an image, sharpening the directional interpolated blocks of pixel data, and optionally clamping the sharpened, directional interpolated blocks of pixel data.

Dynamic Compiler Parallelism Techniques

Granted: January 14, 2016
Application Number: 20160011857
Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.

DETERMINING OVERALL PERFORMANCE CHARACTERISTICS OF A CONCURRENT SOFTWARE APPLICATION

Granted: November 26, 2015
Application Number: 20150339209
One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency…

DYNAMIC YIELD PREDICTION

Granted: September 10, 2015
Application Number: 20150253373
Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a…

MICROELECTRONIC PACKAGE PLATE WITH EDGE RECESSES FOR IMPROVED ALIGNMENT

Granted: September 10, 2015
Application Number: 20150255365
A microelectronic package includes a package substrate with at least one semiconductor die mounted thereon and a plate coupled to the package substrate. The plate is configured with a first recess formed in a first edge of the plate and a second recess formed in a second edge of the plate wherein the first edge and the second edge are formed on opposing sides of the plate. One advantage of the above-described embodiments is that a stiffener plate or heat spreader that is sized to cover…

WEARABLE FINGER RING INPUT DEVICE AND CONTROLLER

Granted: August 27, 2015
Application Number: 20150241976
Systems and methods for remotely providing user input to different electronic devices based on user finger motions and/or gestures. A universal user input device assembles a motion sensor, control logic, a memory and a processor into a substantially ring-shaped housing that is wearable on a finger of a user. The input device can identify an associated external device, establish a communication channel therewith, and provide user input instructions to the external device based on user's…

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING ONE-DIMESIONAL SEARCHES IN TWO-DIMENSIONAL IMAGES

Granted: August 27, 2015
Application Number: 20150243048
A system, method, and computer program product are provided for implementing a search of a digital image along a set of paths. The method includes the steps of selecting a set of paths in an image and identifying at least one feature pixel in the set of paths by comparing gradients for each of the pixels in the set of paths. The set of paths includes at least one line of pixels in the image, and a total number of pixels in the set of paths is less than half of a number of pixels in the…

TECHNIQUES FOR AVOIDING AND REMEDYING DC BIAS BUILDUP ON A FLAT PANEL VARIABLE REFRESH RATE DISPLAY

Granted: August 27, 2015
Application Number: 20150243233
A method for driving a display panel having a variable refresh rate is disclosed. The method comprises receiving a current input frame from an image source. Next, it comprises determining a number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the input frame, and wherein the number of re-scanned frames depends on the minimum refresh interval (MRI) of the display panel. Further, it comprises calculating…

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A HIGH BANDWIDTH BOTTOM PACKAGE

Granted: August 27, 2015
Application Number: 20150243610
A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom…

INTERFACE ANALYSIS FOR VERIFICATION OF DIGITAL CIRCUITS

Granted: August 20, 2015
Application Number: 20150234963
A method for performing an interface analysis. The method includes identifying a first module included in a representation of a digital circuit. The method also includes identifying a first output port associated with the first module. The method further includes identifying a first logic path that extends from the first output port. The method also includes determining that the first logic path extends to a first storage element included in the first module. The method further includes…

PSEUDO-DIFFERENTIAL READ SCHEME FOR DUAL PORT RAM

Granted: August 20, 2015
Application Number: 20150235681
A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global…

WRITE ASSIST SCHEME FOR LOW POWER SRAM

Granted: August 20, 2015
Application Number: 20150235695
A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal…

AUTOMATICALLY PERFORMING A TRADE-OFF BETWEEN VISUAL QUALITY AND LATENCY DURING RENDERING OF A VIDEO/GRAPHICS SEQUENCE

Granted: August 13, 2015
Application Number: 20150228046
A method includes automatically capturing, through a processor of a data processing device communicatively coupled to a memory, one or more parameter(s) related to a visual quality of rendering of a video frame that is part of a sequence on a display unit communicatively coupled to the processor and one or more parameter(s) related to latency associated with the rendering of the video frame on the display unit. The sequence is a video and/or a graphics sequence. The method also includes…

LIQUID CRYSTAL DISPLAY OVERDRIVE INTERPOLATION CIRCUIT AND METHOD

Granted: August 13, 2015
Application Number: 20150228055
A liquid crystal display (LCD) overdrive interpolation circuit and method, and an LCD drive system incorporating the circuit or method. In one embodiment, the circuit includes: (1) a diagonal interpolator operable to perform a diagonal interpolation along a diagonal direction in a lookup table based on TO and FROM gray levels and (2) a further interpolator coupled to the diagonal interpolator and operable to perform a further interpolation based on a result of the diagonal interpolation…

POWER-EFFICIENT STEERABLE DISPLAYS

Granted: August 13, 2015
Application Number: 20150228226
A method for angularly varying backlight illumination of a backlit display device. The method comprises determining at least one subject position and angularly varying a backlight illumination of a displayed image. The backlight illumination is angularly varied based upon and directed towards a determined position of the at least one subject. The angularly varied backlight illumination of the displayed image reduces the backlight illumination of the displayed image that is visible…