Nvidia Patent Grants

Approach for performing improved timing analysis with improved accuracy

Granted: May 23, 2017
Patent Number: 9659139
One embodiment of the present invention includes a method for updating timing parameters after a circuit design change. The method includes, prior to the circuit design change, deriving a value for a first timing parameter based on a signoff timing analysis of a timing arc, and a value for a second timing parameter based on a quick timing analysis of the timing arc; and obtaining a first transition time based on the quick timing analysis. The method further includes, after the circuit…

Programmable graphics processor for multithreaded execution of programs

Granted: May 23, 2017
Patent Number: 9659339
A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The…

System, method, and computer program product for passing attribute structures between shader stages in a graphics pipeline

Granted: May 23, 2017
Patent Number: 9659399
A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit…

System, method, and computer program product for a cavity package-on-package structure

Granted: May 23, 2017
Patent Number: 9659815
A system, method, and computer program product are provided for producing a cavity bottom package of a package-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer including a first set of pads configured to be electrically coupled to a second set of pads of an integrated circuit die. A layer of non-conductive material is applied to the top layer of the bottom package and a cavity is formed in the layer of…

Radio frequency power amplifier including a pulse generator and matching network circuit

Granted: May 23, 2017
Patent Number: 9660599
A system and method are provided for controlling a radio frequency (RF) power amplifier. A magnitude input and a phase input are received for transmission of a RF signal by the RF power amplifier. A digital pulse, having a center position relative to an edge of a reference clock based on the phase input and having a width based on the magnitude input, is generated. The digital pulse is filtered with a resonant matching network to produce the RF signal corresponding to the magnitude input…

Techniques for degrading rendering quality to increase operating time of a computing platform

Granted: May 16, 2017
Patent Number: 9652016
Techniques for degrading rendering performance to extend operating time of a computing platform includes determining a source and a level of power for the computing platform during receipt of the graphics data and rendering of the graphics data. Graphics data is rendered using settings received from the application if the computing platform is not operating from a limited power supply. The graphics data is rendered using one or more sets of graphics processing power conservation…

Software-assisted instruction level execution preemption

Granted: May 16, 2017
Patent Number: 9652282
One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed.…

Texel data structure for graphics processing unit programmable shader and method of operation thereof

Granted: May 16, 2017
Patent Number: 9652815
A graphics processing subsystem and a method of shading are provided. In one embodiment, the subsystem includes: (1) a memory configured to contain a texel data structure according to which multiple primitive texels corresponding to a particular composite texel are contained in a single page of the memory and (2) a graphics processing unit configured to communicate with the memory via a data bus and execute a shader to fetch the multiple primitive texels contained in the single page to…

Selective power gating to extend the lifetime of sleep FETs

Granted: May 9, 2017
Patent Number: 9645635
A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (FETs). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block. When the logic block draws a lower voltage, the zone controller enables a lower number of zones. When the logic block draws a higher voltage, the zone controller enables a greater number of zones. One…

Technique for grouping instructions into independent strands

Granted: May 9, 2017
Patent Number: 9645802
A device compiler and linker is configured to group instructions into different strands for execution by different threads based on the dependence of those instructions on other, long-latency instructions. A thread may execute a strand that includes long-latency instructions, and then hardware resources previously allocated for the execution of that thread may be de-allocated from the thread and re-allocated to another thread. The other thread may then execute another strand while the…

Speculative permission acquisition for shared memory

Granted: May 9, 2017
Patent Number: 9645929
In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.

Time-multiplexed communication protocol for transmitting a command and address between a memory controller and multi-port memory

Granted: May 9, 2017
Patent Number: 9646656
One embodiment sets forth a technique for time-multiplexed communication for transmitting command and address information between a controller and a multi-port memory device over a single connection. Command and address information for each port of the multi-port memory device is time-multiplexed within the controller to produce a single stream of commands and addresses for different memory requests. The single stream of commands and addresses is transmitted by the controller to the…

Predictive current sensing

Granted: May 2, 2017
Patent Number: 9639102
A system and method are provided for estimating current. A current source is configured to generate a current and a pulsed sense enable signal is generated. An estimate of the current is generated and the estimate of the current is updated based on a first signal that is configured to couple the current source to an electric power supply and a second signal that is configured to couple the current source to aloud. A system includes the current source and a current prediction unit. The…

Logarithmic gain adjuster

Granted: May 2, 2017
Patent Number: 9639327
A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a…

Algorithm for vectorization and memory coalescing during compiling

Granted: May 2, 2017
Patent Number: 9639336
One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly…

Indirect function call instructions in a synchronous parallel thread processor

Granted: May 2, 2017
Patent Number: 9639365
An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Instructions for managing a parallel cache hierarchy

Granted: May 2, 2017
Patent Number: 9639479
A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the…

Setting a PCIE Device ID

Granted: May 2, 2017
Patent Number: 9639494
One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One…

Write assist scheme for low power SRAM

Granted: May 2, 2017
Patent Number: 9640249
A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal…

System and method for dynamic frequency estimation for a spread-spectrum digital phase-locked loop

Granted: May 2, 2017
Patent Number: 9641182
A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first…