Nvidia Patent Grants

System and method for allocating memory of differing properties to shared data objects

Granted: July 18, 2017
Patent Number: 9710275
A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage…

Methods and apparatus for auto-throttling encapsulated compute tasks

Granted: July 18, 2017
Patent Number: 9710306
Systems and methods for auto-throttling encapsulated compute tasks. A device driver may configure a parallel processor to execute compute tasks in a number of discrete throttled modes. The device driver may also allocate memory to a plurality of different processing units in a non-throttled mode. The device driver may also allocate memory to a subset of the plurality of processing units in each of the throttling modes. Data structures defined for each task include a flag that instructs…

Mid-primitive graphics execution preemption

Granted: July 18, 2017
Patent Number: 9710874
One embodiment of the present invention sets forth a technique for mid-primitive execution preemption. When preemption is initiated no new instructions are issued, in-flight instructions progress to an execution unit boundary, and the execution state is unloaded from the processing pipeline. The execution units within the processing pipeline, including the coarse rasterization unit complete execution of in-flight instructions and become idle. However, rasterization of a triangle may be…

System and method for enhanced multi-sample anti-aliasing

Granted: July 18, 2017
Patent Number: 9710894
A system and method for enhanced multi-sample anti-aliasing. The method includes determining a sampling pattern corresponding to a pixel and adjusting the sampling pattern based on a visual effect (e.g., post-processing visual effect). The method further includes accessing a first plurality of samples based on the sampling pattern. The first plurality of samples may comprise a second plurality of samples within the pixel and a third plurality of pixels outside of the pixel. The method…

Techniques for avoiding and remedying DC bias buildup on a flat panel variable refresh rate display

Granted: July 18, 2017
Patent Number: 9711099
A method for driving a display panel having a variable refresh rate is disclosed. The method comprises receiving a current input frame from an image source. Next, it comprises determining a number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the input frame, and wherein the number of re-scanned frames depends on the minimum refresh interval (MRI) of the display panel. Further, it comprises calculating…

System and method for image processing

Granted: July 11, 2017
Patent Number: 9704212
A system and method for image processing are provided. The system comprises a main computing device and a secondary computing device. The main computing device comprises a main graphics card and a main central processing unit, and the secondary computing device comprises a secondary graphics card and a secondary central processing unit. The main computing device is configured to detect the secondary computing device. The main central processing unit is configured to send a request to…

Technique for performing memory access operations via texture hardware

Granted: July 4, 2017
Patent Number: 9697006
A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address…

Application programming interface to enable the construction of pipeline parallel programs

Granted: July 4, 2017
Patent Number: 9697044
An application programming interface (API) provides various software constructs that allow a developer to assemble a processing pipeline having arbitrary structure and complexity. Once assembled, the processing pipeline is configured to include a set of interconnected pipestages. Those pipestages are associated with one or more different CTAs that may execute in parallel with one another on a parallel processing unit. The developer specifies the configuration of the pipestages, including…

Alpha-to-coverage using virtual samples

Granted: July 4, 2017
Patent Number: 9697641
One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An…

Selecting hash values based on matrix rank

Granted: June 27, 2017
Patent Number: 9690715
One embodiment of the present invention includes a hash selector that facilitates performing effective hashing operations. In operation, the hash selector creates a transformation matrix that reflects specific optimization criteria. For each hash value, the hash selector generates a potential hash value and then computes the rank of a submatrix included in the transformation matrix. Based on this rank in conjunction with the optimization criteria, the hash selector either re-generates…

Managing state transitions of a data connector using a finite state machine

Granted: June 27, 2017
Patent Number: 9690736
A microprocessor within a processing unit is configured to manage to operation of a finite state machine (FSM) that, in turn, manages the operation of a data connector. The FSM may be a hardwired chip component that adheres to a communication protocol associated with the data connector. The microprocessor is configured to execute a software application in order to (i) apply configuration changes to the processing unit during state transitions initiated by the FSM and (ii) cause the FSM…

Determining overall performance characteristics of a concurrent software application

Granted: June 20, 2017
Patent Number: 9684581
One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency…

Pixel serialization to improve conservative depth estimation

Granted: June 20, 2017
Patent Number: 9684998
One embodiment includes determining a first z-range for a first portion of a coarse raster tile, where the first portion includes a plurality of pixels having a first set of pixel locations, retrieving from a memory a corresponding z-range related to a second set of pixel locations associated with the coarse raster tile, where the first set of pixel locations comprises a subset of the second set of pixel locations, and comparing the first z-range to the corresponding z-range to determine…

Sequential access memory with master-slave latch pairs and method of operating

Granted: June 20, 2017
Patent Number: 9685207
A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Efficiency-based clock frequency adjustment

Granted: June 13, 2017
Patent Number: 9678529
One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a…

Allocating memory for local variables of a multi-threaded program for execution in a single-threaded environment

Granted: June 13, 2017
Patent Number: 9678775
Computer code written to execute on a multi-threaded computing environment is transformed into code designed to execute on a single-threaded computing environment and simulate concurrent executing threads. Optimization techniques during the transformation process are utilized to identify local variables for scalar expansion. A first set of local variables is defined that includes those local variables in the code identified as “Downward exposed Defined” (DD). A second set of local…

Approach for context switching of lock-bit protected memory

Granted: June 13, 2017
Patent Number: 9678897
A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming…

Compressing graphics data rendered on a primary computer for transmission to a remote computer

Granted: June 13, 2017
Patent Number: 9679530
One embodiment of the present invention sets forth a method for compressing via a pixel shader color information associated with a line of pixels. An intermediary representation of an uncompressed stream of color information is first generated that indicates, for each pixel, whether a previous adjacent pixel shares color information with the pixel. A set of cascading buffers is then generated based on intermediary representation, where each cascading buffer represents a number of unique…

Stylus tool with deformable tip

Granted: June 6, 2017
Patent Number: 9671877
A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a chisel shaped tip disposed at the first end of the body is provided. The chisel shaped tip includes a deformable material such that the chisel shaped tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the chisel shaped tip. The chisel shaped tip is…

Pausible bisynchronous FIFO

Granted: June 6, 2017
Patent Number: 9672008
A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is…