Nvidia Patent Grants

Branch prediction power reduction

Granted: January 17, 2017
Patent Number: 9547358
In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state…

Method and system for providing shared memory access to graphics processing unit processes

Granted: January 17, 2017
Patent Number: 9547535
One or more embodiments of the invention set forth techniques to create a process in a graphical processing unit (GPU) that has access to memory buffers in the system memory of a computer system that are shared among a plurality of GPUs in the computer system. The GPU of the process is able to engage in Direct Memory Access (DMA) with any of the shared memory buffers thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such…

Translation lookaside buffer entry systems and methods

Granted: January 17, 2017
Patent Number: 9547602
Presented systems and methods can facilitate efficient information storage and tracking operations, including translation look aside buffer operations. In one embodiment, the systems and methods effectively allow the caching of invalid entries (with the attendant benefits e.g., regarding power, resource usage, stalls, etc), while maintaining the illusion that the TLBs do not in fact cache invalid entries (e.g., act in compliance with architectural rules). In one exemplary implementation,…

System, method, and computer program product for pre-filtered anti-aliasing with deferred shading

Granted: January 17, 2017
Patent Number: 9547931
A system, method, and computer program product are provided for generating anti-aliased images. The method includes the steps of assigning one or more samples to a plurality of clusters, each cluster in the plurality of clusters corresponding to an aggregate stored in an aggregate geometry buffer, where each of the one or more samples is covered by a visible fragment and rasterizing three-dimensional geometry to generate material parameters for each sample of the one or more samples. For…

Splitting bounding volumes of primitives

Granted: January 17, 2017
Patent Number: 9547932
A system, method, and computer program product are provided for splitting primitives. A plurality of primitives is received for a scene and a pre-determined plane that intersects the scene is identified. Bounding volumes of the plurality of primitives that are intersected by the pre-determined plane are split, where a bounding volume that encloses each intersected primitive of the plurality of primitives is split into a first bounding volume and a second bounding volume at an…

System and method for creating a video frame from a single video field

Granted: January 17, 2017
Patent Number: 9549147
A system and method of producing a frame of a video image from an interlaced field. In one embodiment, the method includes: (1) creating an equal-intensity trace from present samples in the field, (2) recognizing an equal-intensity path in the equal-intensity trace, (3) at least partially straightening the equal-intensity path and (4) using the equal-intensity path to determine an intensity value for a missing sample in the frame.

Heuristics for improving performance in a tile-based architecture

Granted: January 10, 2017
Patent Number: 9542189
One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second…

Tokenized streams for concurrent execution between asymmetric multiprocessors

Granted: January 10, 2017
Patent Number: 9542192
A method for executing an application program using streams. A device driver receives a first command within an application program and parses the first command to identify a first stream token that is associated with a first stream. The device driver checks a memory location associated with the first stream for a first semaphore, and determines whether the first semaphore has been released. Once the first semaphore has been released, a second command within the application program is…

Parallel dynamic memory allocation using a lock-free FIFO

Granted: January 10, 2017
Patent Number: 9542227
One embodiment of the present invention sets forth a technique for dynamically allocating memory using one or more lock-free FIFOs. One or more lock-free FIFOs are populated with FIFO nodes, where each FIFO node represents a memory allocation of a predetermined size. Each particular lock-free FIFO includes memory allocations of a single size. Different lock-free FIFOs may include memory allocations for different sizes to service allocation requests for different size memory allocations.…

Memory space mapping techniques for server based graphics processing

Granted: January 10, 2017
Patent Number: 9542715
The server based graphics processing techniques, describer herein, include loading a given instance of a guest shim layer and loading a given instance of a guest display device interface that calls back into the given instance of the guest shim layer, in response to loading the given instance of the guest shim layer, wherein the guest shim layer and the guest display device interface are executing under control of a virtual machine guest operating system. The given instance of the shim…

SRAM core cell design with write assist

Granted: January 10, 2017
Patent Number: 9542992
A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is…

System, method, and computer program product for collecting execution statistics for graphics processing unit workloads

Granted: January 3, 2017
Patent Number: 9535815
A system, method, and computer program product are provided for collecting trace information based on a computational workload. The method includes the steps of compiling source code to generate a program, launching a workload to be executed by the parallel processing unit, collecting one or more records of trace information associated with a plurality of threads configured to execute the program, and correlating the one or more records to one or more corresponding instructions included…

Using a geometry shader for variable input and output algorithms

Granted: January 3, 2017
Patent Number: 9536275
A system and method uses the capabilities of a geometry shader unit within the multi-threaded graphics processor to implement algorithms with variable input and output.

Distributing primitives to multiple rasterizers

Granted: January 3, 2017
Patent Number: 9536341
One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or…

Passive cooling system integrated into a printed circuit board for cooling electronic components

Granted: January 3, 2017
Patent Number: 9538633
A passive cooling system is provided for dissipating heat from an electronic component. The system includes a printed circuit board including a first dielectric layer and a first conductive layer, an electronic component coupled to the printed circuit board via a plurality of electrical contacts, and a cooling component thermally coupled to the electronic component through the first conductive layer by a micro via thermal array.

Methods and apparatus for reducing perceived pen-to-ink latency on touchpad devices

Granted: December 27, 2016
Patent Number: 9529525
A method for reducing line display latency on a touchpad device is disclosed. The method comprises storing information regarding a plurality of prior touch events on a touch screen of the touchpad device into an event buffer. It further comprises determining an average speed and a predicted direction of motion of a user interaction with the touch screen using the plurality of prior touch events. Next, it comprises calculating a first prediction point using the average speed, the…

Techniques for balancing accesses to memory having different memory types

Granted: December 27, 2016
Patent Number: 9529712
Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

Alternate reduction ratios and threshold mechanisms for framebuffer compression

Granted: December 27, 2016
Patent Number: 9530189
A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a…

Low-profile chip package with modified heat spreader

Granted: December 27, 2016
Patent Number: 9530714
An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced…

Load balancing in a system with multi-graphics processors and multi-display systems

Granted: December 20, 2016
Patent Number: 9524138
In typical embodiments a three GPU configuration is provided comprising three discrete video cards, each connected to a standard monitor placed horizontally for a 3× horizontal resolution. In this configuration, depending on the load on each GPU, the vertical split lines are dynamically adjusted. To adjust the load balancing according to these virtual split lines, the rendering clip rectangle of each GPU is adjusted, in order to reduce the number of pixels rendered by the heavily loaded…