Nvidia Patent Grants

Method and system for resolving thread divergences

Granted: March 28, 2017
Patent Number: 9606808
A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from…

Method and apparatus for watermarking binary computer code

Granted: March 28, 2017
Patent Number: 9607133
A method and apparatus for inserting a watermark into a compiled computer program. A location process specifies an insertion point in the compiled program and a watermark generating process inserts a watermark, based on data to be encoded, into the program at the insertion point. The location process is also utilized to specify the location of watermark data to be decoded.

Variable-width differential memory compression

Granted: March 28, 2017
Patent Number: 9607407
A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. Furthermore; the method can include performing packing that includes utilizing varying sized bit fields to produce a compressed representation.

Hardware command training for memory using write leveling mechanism

Granted: March 28, 2017
Patent Number: 9607714
A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure…

Technique for performing arbitrary width integer arithmetic operations using fixed width elements

Granted: March 21, 2017
Patent Number: 9600235
One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One…

Parallel multicolor incomplete LU factorization preconditioning processor and method of use thereof

Granted: March 21, 2017
Patent Number: 9600446
A preconditioner processor and a method of computing a preconditioning matrix. In one embodiment, the preconditioner processor has parallel computing pipelines including: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an incomplete lower triangle, upper triangle factorization (ILU) computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning…

Hierarchical hash tables for SIMT processing and a method of establishing hierarchical hash tables

Granted: March 21, 2017
Patent Number: 9600852
A graphical processing unit having an implementation of a hierarchical hash table thereon, a method of establishing a hierarchical hash table in a graphics processing unit and GPU computing system are disclosed herein. In one embodiment, the graphics processing unit includes: (1) a plurality of parallel processors, wherein each of the plurality of parallel processors includes parallel processing cores, a shared memory coupled to each of the parallel processing cores, and registers,…

Clock generation circuit that tracks critical path across process, voltage and temperature variation

Granted: March 21, 2017
Patent Number: 9602083
Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving…

Estimating channel information

Granted: March 21, 2017
Patent Number: 9602230
Disclosed is a method of providing channel state information for a desired downlink channel of a wireless communication system. In a configuration phase, the method comprises receiving on a signaling channel configuration information comprising an identifier of an interference source and an association which associates the identifier with at least one resource element not used for transmission on the desired downlink channel. In an estimation phase, the method comprises estimating…

Slice ordering for video encoding

Granted: March 21, 2017
Patent Number: 9602821
For encoding, a frame of video data can be segregated into macroblocks, which can be segregated into slices, which in turn can be segregated into slice groups. A macroblock identifier (ID) can be associated with each of the macroblocks. When at least one slice from each of the slice groups has been encoded, the macroblock IDs associated with the encoded slices can be compared to determine an order in which the encoded slices are to be placed in an access unit for the frame. Of the…

Virtualization of chip enables

Granted: March 14, 2017
Patent Number: 9594675
Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.

Speculative memory controller

Granted: March 14, 2017
Patent Number: 9594700
A method and a system are provided for controlling memory accesses. Memory access requests including at least a first speculative memory access request and a first non-speculative memory access request are received and a memory access request is selected from the memory access requests. A memory access command is generated to process the selected memory access request.

Load/store operations in texture hardware

Granted: March 14, 2017
Patent Number: 9595075
Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then…

Single element dual-feed antennas and an electronic device including the same

Granted: March 14, 2017
Patent Number: 9595759
Provided is an antenna. The antenna, in this aspect, includes an inverted-F GPS antenna structure, the inverted-F GPS antenna structure embodying a GPS feed element, a GPS extending arm, and a ground element. The antenna, in this aspect, further includes a loop WiFi antenna structure, the loop WiFi antenna structure embodying a WiFi feed element, the ground element, and a WiFi connecting arm coupling the WiFi feed element to the ground element. In this particular aspect, the ground…

In-rush current limiting switch control

Granted: March 14, 2017
Patent Number: 9595827
A subsystem is configured to apply a voltage source to a gated circuit domain in a manner that limits in-rush current and affords minimal time delay. A control signal turns on a wake-up switch that connects the voltage source to the domain. The equivalent series resistance of the wake-up switch has a magnitude that limits the transient charge current to the gated domain. A digital control circuit monitors the resulting rising domain voltage and determines when the domain voltage reaches…

System, method, and computer program product for a pinlight see-through near-eye display

Granted: March 14, 2017
Patent Number: 9594247
A system, method, and computer program product are provided for implementing a pinlight see-through near-eye display. Light cones configured to substantially fill a field-of-view corresponding to a pupil are generated by an array of pinlights positioned between a near focus plane and the pupil. Overlap regions where two of more light cones intersect at a display layer positioned between the array of pinlights and the pupil are determined. The two or more light cones are modulated based…

Method and system for distributing work batches to processing units based on a number of enabled streaming multiprocessors

Granted: March 14, 2017
Patent Number: 9594599
A work distribution unit distributes work batches to general processing clusters (GPCs) based on the number of streaming multiprocessors included in each GPC. Advantageously, each GPC receives an amount of work that is proportional to the amount of processing power afforded by the GPC. Embodiments include a method for distributing batches of processing tasks to two or more general processing clusters (GPCs), including the steps of updating a counter value for each of the two or more GPCs…

Microcontroller for memory management unit

Granted: March 7, 2017
Patent Number: 9588903
One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page…

Methods to facilitate primitive batching

Granted: March 7, 2017
Patent Number: 9589310
One embodiment of the present invention sets forth a technique for splitting a set of vertices into a plurality of batches for processing. The method includes receiving one or more primitives each containing an associated set of vertices. For each of the one or more primitives, one or more vertices are gathered from the set of vertices, the vertices are arranged into one or more batches, the batch is routed to a processing pipeline line to process each batch as a separate primitive, and…

Unified position based solver for visual effects

Granted: March 7, 2017
Patent Number: 9589383
A method for simulating visual effects is disclosed. The method comprises modeling each visual effect within a simulation as a set of associated particles with associated constraints applicable thereto. It also comprises predicting first velocities and first positions of a plurality of particles being used to simulate a visual effect based on an external force applied to the plurality of particles. Next, it comprises identifying a set of neighboring particles for each of the plurality of…