Nvidia Patent Grants

Selecting hash values based on matrix rank

Granted: June 27, 2017
Patent Number: 9690715
One embodiment of the present invention includes a hash selector that facilitates performing effective hashing operations. In operation, the hash selector creates a transformation matrix that reflects specific optimization criteria. For each hash value, the hash selector generates a potential hash value and then computes the rank of a submatrix included in the transformation matrix. Based on this rank in conjunction with the optimization criteria, the hash selector either re-generates…

Managing state transitions of a data connector using a finite state machine

Granted: June 27, 2017
Patent Number: 9690736
A microprocessor within a processing unit is configured to manage to operation of a finite state machine (FSM) that, in turn, manages the operation of a data connector. The FSM may be a hardwired chip component that adheres to a communication protocol associated with the data connector. The microprocessor is configured to execute a software application in order to (i) apply configuration changes to the processing unit during state transitions initiated by the FSM and (ii) cause the FSM…

Determining overall performance characteristics of a concurrent software application

Granted: June 20, 2017
Patent Number: 9684581
One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency…

Pixel serialization to improve conservative depth estimation

Granted: June 20, 2017
Patent Number: 9684998
One embodiment includes determining a first z-range for a first portion of a coarse raster tile, where the first portion includes a plurality of pixels having a first set of pixel locations, retrieving from a memory a corresponding z-range related to a second set of pixel locations associated with the coarse raster tile, where the first set of pixel locations comprises a subset of the second set of pixel locations, and comparing the first z-range to the corresponding z-range to determine…

Sequential access memory with master-slave latch pairs and method of operating

Granted: June 20, 2017
Patent Number: 9685207
A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Efficiency-based clock frequency adjustment

Granted: June 13, 2017
Patent Number: 9678529
One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a…

Allocating memory for local variables of a multi-threaded program for execution in a single-threaded environment

Granted: June 13, 2017
Patent Number: 9678775
Computer code written to execute on a multi-threaded computing environment is transformed into code designed to execute on a single-threaded computing environment and simulate concurrent executing threads. Optimization techniques during the transformation process are utilized to identify local variables for scalar expansion. A first set of local variables is defined that includes those local variables in the code identified as “Downward exposed Defined” (DD). A second set of local…

Approach for context switching of lock-bit protected memory

Granted: June 13, 2017
Patent Number: 9678897
A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming…

Compressing graphics data rendered on a primary computer for transmission to a remote computer

Granted: June 13, 2017
Patent Number: 9679530
One embodiment of the present invention sets forth a method for compressing via a pixel shader color information associated with a line of pixels. An intermediary representation of an uncompressed stream of color information is first generated that indicates, for each pixel, whether a previous adjacent pixel shares color information with the pixel. A set of cascading buffers is then generated based on intermediary representation, where each cascading buffer represents a number of unique…

Stylus tool with deformable tip

Granted: June 6, 2017
Patent Number: 9671877
A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a chisel shaped tip disposed at the first end of the body is provided. The chisel shaped tip includes a deformable material such that the chisel shaped tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the chisel shaped tip. The chisel shaped tip is…

Pausible bisynchronous FIFO

Granted: June 6, 2017
Patent Number: 9672008
A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is…

Stereo viewpoint graphics processing subsystem and method of sharing geometry data between stereo images in screen-spaced processing

Granted: June 6, 2017
Patent Number: 9672653
A stereo viewpoint graphics processing subsystem and a method of sharing geometry data between stereo images in screen-space processing. One embodiment of the stereo viewpoint graphics processing subsystem configured to render a scene includes: (1) stereo frame buffers configured to contain respective pixel-wise rendered scene data for stereo images, and (2) a sharing decision circuit operable to determine when to share geometric data between the stereo frame buffers for carrying out…

Simultaneous execution of compute and graphics applications

Granted: May 30, 2017
Patent Number: 9665920
One embodiment of the present invention sets forth a technique for distributing graphics commands and atomic commands to a color processing unit (CROP) in an efficient manner. The interleaving mechanism determines, at each clock cycle, which graphics command(s) or atomic command(s) is transmitted to the CROP based on different factors. First, the interleaving mechanism ensures that atomic commands or graphics commands associated with a multi-transaction command stream are processed…

System, method, and computer program product for redistributing a multi-sample processing workload between threads

Granted: May 30, 2017
Patent Number: 9665958
A system, method, and computer program product are provided for redistributing multi-sample processing workloads between threads. A workload for a plurality of multi-sample pixels is received and each thread in a parallel thread group is associated with a corresponding multi-sample pixel of the plurality of pixels. The workload is redistributed between the threads in the parallel thread group based on a characteristic of the workload and the workload is processed by the parallel thread…

Data path and instruction set for packed pixel operations for video processing

Granted: May 30, 2017
Patent Number: 9665969
One embodiment of the present invention discloses a method for processing video data within a video data processing path of a processing unit. The video data processing path includes three stages. In the first stage, source operands are extracted from a local register file and are ordered to map efficiently onto the downstream data path. In the second stage, arithmetic operations are performed on the source operands based on video processing instructions to generate intermediate results.…

System, method, and computer program product for a switch mode current balancing rail merge circuit

Granted: May 30, 2017
Patent Number: 9667068
A system, method, and computer program product are provided for merging two or more supply rails into a merged supply rail. The method comprises receiving two or more current measurement signals associated with two or more supply rails, selecting one supply rail from the two or more supply rails, based on the current measurement signals, and enabling the selected supply rail to source current into a merged supply rail.

Latch and flip-flop circuits with shared clock-enabled supply nodes

Granted: May 30, 2017
Patent Number: 9667230
A method for operating a latch and a latch circuit are disclosed. The latch circuit comprises a storage sub-circuit, a propagation sub-circuit, and a shared clock-enabled transistor. The storage sub-circuit is configured to capture a level of an input signal when a clock signal transitions from first level to a second level and hold the captured level to generate an output signal while the clock signal is at the second level. The propagation sub-circuit is configured to enable a path…

Managing SIM indications

Granted: May 30, 2017
Patent Number: 9667668
One aspect provides a method of handling a proactive indication received from a subscriber identity module at a modem, the modem being connected to a terminal equipment via a command interface. The method comprises receiving, at a modem processor, the proactive indication from the subscriber identity module. The method further comprises determining that the indication is to be handled by the modem processor. The method further comprises a modem processor transmitting a display command…

Dynamic public warning system deactivation

Granted: May 30, 2017
Patent Number: 9668284
One aspect provides a method of operating a modem at a terminal. The modem is arranged to store one or more message identifier. Each of the one or more message identifier identifies a type of message that the modem is arranged to act upon when received on a broadcast channel from a communications network. The method comprises detecting a country that the terminal is located in. The method further comprises determining if the detected country is a country in which a public warning system…

Approach for performing improved timing analysis with improved accuracy

Granted: May 23, 2017
Patent Number: 9659139
One embodiment of the present invention includes a method for updating timing parameters after a circuit design change. The method includes, prior to the circuit design change, deriving a value for a first timing parameter based on a signoff timing analysis of a timing arc, and a value for a second timing parameter based on a quick timing analysis of the timing arc; and obtaining a first transition time based on the quick timing analysis. The method further includes, after the circuit…