Adapter board for stacking Ball-Grid-Array (BGA) chips
Granted: October 24, 2006
Patent Number:
7126829
Electronic devices packaged with arrayed solder balls, leads, or pads, such as Ball Grid Array (BGA) devices, are stacked together. Each stack has a bottom adapter card with metal contacts on a top surface in an array to match the array of solder balls of a lower BGA package, and final bonding pads on a bottom surface that are soldered to an underlying motherboard or printed-circuit board (PCB). An upper BGA package has its solder balls connected to a matching array of metal contacts on…
Dynamic PCI-bus pre-fetch with separate counters for commands of commands of different data-transfer lengths
Granted: September 12, 2006
Patent Number:
7107384
A Peripheral Component Interconnect (PCI) bridge between two buses prefetches read data into a cache. The number of cache lines to prefetch is predicted by a prefetch counter. One prefetch counter is kept for each type of memory-read command: basic memory-read (MR), memory-read-line (MRL) that reads a cache line, and memory-read-multiple (MRM) that reads multiple cache lines. For each type of read command, counters are kept of the number of completed commands, bus-disconnects (indicating…
Manufacturing process for a surface-mount metal-cavity package for an oscillator crystal blank
Granted: July 18, 2006
Patent Number:
7076870
A surface-mount package for an oscillator crystal blank is made from a metal sheet substrate. Half-etched cavities are formed on one side of the sheet. The half-etched cavities are filled in with an insulator. The center of the insulator is drilled until metal is reached, leaving insulator on the sidewalls of the resulting drilled via. The bottom of the drilled via is plated with a contact metal such as nickel-gold, and then the entire drilled via is filled in with metal such as copper…
Memory module with dynamic termination using bus switches timed by memory clock and chip select
Granted: June 27, 2006
Patent Number:
7068064
A low-power memory module has an active termination circuit at each end of critical signal traces. The dynamic termination circuit has a low-value resistor that is connected to a termination voltage by a transmission gate that is turned on by a switch signal. The switch signal is activated when the memory module is selected by a chip-select signal, and when a time window is open. The time window is generated from the clock to synchronous DRAMs on the memory module. The time window can be…
4X crystal frequency multiplier with op amp buffer between 2X multiplier stages
Granted: May 30, 2006
Patent Number:
7053725
A frequency-multiplying circuit generates a multiple of the fundamental frequency of a crystal that oscillates. A first differential multiplier is coupled to the crystal nodes and generates a frequency-doubled output. The frequency-doubled output is applied to an op amp that buffers the output and compares it to a reference to generate a pair of differential buffered signals. The differential buffered signals are applied to a second differential multiplier that generates a final…
Differential clock signals encoded with data
Granted: March 28, 2006
Patent Number:
7020208
The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock…
CMOS voltage-controlled oscillator (VCO) with a current-adaptive resistor for improved linearity
Granted: March 21, 2006
Patent Number:
7015766
A voltage-controlled oscillator (VCO) for a phase-locked loop (PLL) has improved bandwidth and performance at lower frequency. A variable current source supplies a current to an internal oscillator-power node. The current varies with the VCO input voltage. The internal oscillator-power node drives the sources of p-channel transistors in inverter stages in the ring oscillator. The variable current causes the internal oscillator-power node's voltage to vary, which varies the output…
Current-mirrored crystal-oscillator circuit without feedback to reduce power consumption
Granted: February 21, 2006
Patent Number:
7002422
An oscillator inverter circuit has an input at a first crystal node and drives a second crystal node of a crystal oscillator. The first node is lightly loaded by a gate of an input transistor that generates a buffered node. The buffered node voltage is converted to a varying current by a converter transistor. Another varying current through upper and lower amplifier transistors are mirrored to upper and lower current mirror transistors. The gate and drain of the lower current mirror…
Crystal clock generator operating at third overtone of crystal's fundamental frequency
Granted: February 21, 2006
Patent Number:
7002423
A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a…
Active ESD shunt with transistor feedback to reduce latch-up susceptibility
Granted: January 24, 2006
Patent Number:
6989979
A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts…
Substrate-sensing voltage sensor for voltage comparator with voltage-to-current converters for both reference and input voltages
Granted: January 24, 2006
Patent Number:
6989692
A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-input voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the…
Reduced-capacitance bus switch in isolated P-well shorted to source and drain during switching
Granted: November 15, 2005
Patent Number:
6965253
A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not…
Accurate voltage comparator with voltage-to-current converters for both reference and input voltages
Granted: September 6, 2005
Patent Number:
6940318
A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-in-put voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the…
Self-biasing differential buffer with transmission-gate bias generator
Granted: August 16, 2005
Patent Number:
6930550
A self-biasing differential buffer generates a self-bias voltage from its inputs. A first amplifier receives a first input signal on gates of four transistors—p and n-channel drive transistors in a drive branch and p and n-channel bias-generating transistors in a bias-generating branch. Current source and current sink transistors source and sink current to both branches. The drains of the drive transistors drive a differential output, while the drains of the bias-generating transistors…
Trace-impedance matching at junctions of multi-load signal traces to eliminate termination
Granted: August 9, 2005
Patent Number:
6927992
A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match, reflections caused by the junction are minimized or eliminated. The input impedance can match by being within 20% of the equivalent impedance of the branch lines. The equivalent impedance of branches is the reciprocal of the…
Divide-by-X.5 circuit with frequency doubler and differential oscillator
Granted: April 19, 2005
Patent Number:
6882229
A divide by X.5 circuit can be implemented as a divided by 1.5 circuit. A phase-locked loop (PLL) has a quadrature voltage-controlled oscillator (VCO) that generates four phases offset at 0, 90, 180, and 270 degrees. Differential signals from the VCO are converted to single-ended VCO clocks that drive four divide-by-3 circuits, each clocked by one of the four phases of the VCO clocks. Resets to the divide-by-3 circuits are staggered to activate each divide-by-3 circuit synchronously with…
Stacked-NMOS-triggered SCR device for ESD-protection
Granted: March 15, 2005
Patent Number:
6867957
Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on…
Double-data rate phase-locked-loop with phase aligners to reduce clock skew
Granted: February 22, 2005
Patent Number:
6859109
A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced…
Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay
Granted: January 11, 2005
Patent Number:
6842059
A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the…
CMOS differential input buffer with source-follower input clamps
Granted: October 5, 2004
Patent Number:
6801080
A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest…
