METHODS AND APPARATUS FOR A HIGH PERFORMANCE MESSAGING ENGINE INTEGRATED WITHIN A PCIe SWITCH
Granted: October 1, 2015
Application Number:
20150281126
A method of transferring data over a switch fabric with at least one switch with an embedded network class endpoint device is provided. At a device transmit driver a transfer command is received to transfer a message. If the message length is less than a threshold the message is pushed. If the message length is greater than the threshold, the message is pulled.
REMOTE BOOTING OVER PCI EXPRESS USING SYNTHETIC REMOTE BOOT CAPABILITY
Granted: September 10, 2015
Application Number:
20150254082
A method of remote booting over PCI Express using a synthetic remote boot capability is provided. A management host software system intercepts probe requests from a host and provided information required for a remote boot. The management host software system may include expansion ROM information to support different host architectures. A synthetic device booting capability may be shown to a host, including the expansion ROM information. Additional support for DHCP and TFTP may be…
TUNNELED WINDOW CONNECTION FOR PROGRAMMED INPUT OUTPUT TRANSFERS OVER A SWITCH FABRIC
Granted: May 7, 2015
Application Number:
20150127878
Tunneled window connections are utilized in a switch fabric to perform programmed input output transfers. The window connections are based on global IDs. A management entity may enforce the tunneled window connections, improving security.
MULTI-PATH ID ROUTING IN A PCIE EXPRESS FABRIC ENVIRONMENT
Granted: August 21, 2014
Application Number:
20140237156
PCIe is a point-to-point protocol. A PCIe switch fabric has multi-path routing supported by adding an ID routing prefix to a packet entering the switch fabric. The routing is converted within the switch fabric from address routing to ID routing, where the ID is within a Global Space of the switch fabric. Rules are provided to select optimum routes for packets within the switch fabric, including rules for ordered traffic, unordered traffic, and for utilizing congestion feedback. In one…
METHOD AND APPARATUS FOR SECURING AND SEGREGATING HOST TO HOST MESSAGING ON PCIE FABRIC
Granted: May 1, 2014
Application Number:
20140122765
A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.
MULTIPLE SEAL-RING STRUCTURE FOR THE DESIGN, FABRICATION, AND PACKAGING OF INTEGRATED CIRCUITS
Granted: February 6, 2014
Application Number:
20140035106
A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.
Signal Processing of Multiple Streams
Granted: November 21, 2013
Application Number:
20130308656
Embodiments of methods, apparatuses, and systems for signal processing of multiple input signals to control peak amplitudes of a combined signal are disclosed. One method includes receiving a plurality of input signals, generating a combined signal, the combined signal comprising a plurality of sub-channels, wherein each sub-channel includes a representation of at least a portion of at least one of the plurality of input signals, and processing the representation of the least a portion…
CLOCK RECOVERY SYSTEM
Granted: August 22, 2013
Application Number:
20130214829
In a first embodiment of the present invention, a clock recovery system is provided comprising: a phase comparator; an integrator coupled to the phase comparator; a numerically controlled oscillator coupled to the integrator; and a mixer coupled to the numerically controlled oscillator and to the phase comparator.
GENERATING UNIQUE RANDOM NUMBERS FOR MULTIPLE INSTANTIATIONS
Granted: May 23, 2013
Application Number:
20130132453
In a first embodiment of the present invention, a method for generating a random number for an instance of a hardware description language definition is provided, the method comprising: generating a unique signature for the instance; applying a message digest generation process on the unique signature to arrive at a message digest having a fixed length; and applying a random number generation process on the message digest.
Transceiver Spectrum Control for Cross-Talk Mitigation
Granted: March 21, 2013
Application Number:
20130070823
Embodiments of methods, apparatuses, and systems for preprocessing a transmit signal of a transceiver are disclosed. One method includes estimating parameters of a communication link between the transceiver and a link partner transceiver, estimating cross-talk coupling of the transceiver to at least one other transceiver, and adjusting at least one of a transmit power or a transmit signal waveform based on the estimated parameters and estimated cross-talk. One apparatus includes a…
PCI EXPRESS SWITCH WITH LOGICAL DEVICE CAPABILITY
Granted: January 24, 2013
Application Number:
20130024595
A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the…
THREE DIMENSIONAL FAT TREE NETWORKS
Granted: January 10, 2013
Application Number:
20130010636
In a first embodiment of the present invention, a non-blocking switch fabric is provided comprising: a first set of intra-domain switches; a second set of intra-domain switches; a set of inter-domain switches located centrally between the first set of intra-domain switches and the second set of intra-domain switches, wherein each of the ports of each of the inter-domain switches is connected to an intra-domain switch from the first or second set of intra-domain switches.
SINGLE PIPE NON-BLOCKING ARCHITECTURE
Granted: January 10, 2013
Application Number:
20130013840
A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is…
AUTOMATIC REFERENCE FREQUENCY COMPENSATION
Granted: August 23, 2012
Application Number:
20120216066
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device…
SUPPORTING GLOBAL INPUT/OUTPUT INTERCONNECT FEATURES ON PORTS OF A MIDPOINT DEVICE
Granted: August 23, 2012
Application Number:
20120215948
In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether…
PARALLEL PACKETIZED INTERCONNECT WITH SIMPLIFIED DATA LINK LAYER
Granted: July 5, 2012
Application Number:
20120173945
In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting…
SHARING MULTIPLE VIRTUAL FUNCTIONS TO A HOST USING A PSEUDO PHYSICAL FUNCTION
Granted: June 28, 2012
Application Number:
20120167085
A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the…
MULTI-ROOT SHARING OF SINGLE-ROOT INPUT/OUTPUT VIRTUALIZATION
Granted: June 28, 2012
Application Number:
20120166690
In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with…
Adjustable Latency Transceiver Processing
Granted: June 7, 2012
Application Number:
20120140797
Embodiments of methods, apparatuses and systems for transceiver processing are disclosed. One method includes a transceiver receiving a data stream from a link partner transceiver. A link parameter of a link between the transceiver and the link partner transceiver is determined. Allocation of transceiver processing between high-latency processing and low-latency processing is based at least in part on the link parameter.
DYNAMIC HOST CLOCK COMPENSATION
Granted: June 7, 2012
Application Number:
20120140781
In accordance with a first embodiment of the present invention, a method for improving synchronization of communications between a first port and a second port is provided, the method performed at the first port and comprising: inserting skip symbols into a transmission stream for transmissions from the first port to the second port, wherein the skip symbols are inserted at a first average frequency level; detecting a lack of synchronization between the first port and the second port;…
