PLX Technology Patent Grants

Reducing transmit signal components of a receive signal of a transceiver using a shared DAC architecture

Granted: August 28, 2012
Patent Number: 8254490
Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One embodiment of an apparatus includes a transceiver that simultaneously transmits a transmit signal and receives a receive signal. The transceiver includes a transmit DAC that generates the transmit signal based on a transmit digital signal stream. The transmit DAC includes a plurality of transmit DAC circuit elements, and a plurality of transmit DAC switches…

Efficient decoding

Granted: July 31, 2012
Patent Number: 8234550
A decoder includes circuitry for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the…

Automatic reference frequency compensation

Granted: June 12, 2012
Patent Number: 8201010
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device…

Supporting global input/output interconnect features on ports of a midpoint device

Granted: June 5, 2012
Patent Number: 8196013
In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether…

Automated regression failure management system

Granted: March 27, 2012
Patent Number: 8145949
In a first embodiment of the present invention, a method for performing regression testing on a simulated hardware is provided, the method comprising: scanning a defect database for fixed signatures; retrieving all tests in a failing instance database that correspond to the fixed signatures from the defect database; running one or more of the retrieved tests; determining if any of the retrieved tests failed during running; and for any retrieved test that failed during running, refiling…

Read control in a computer I/O interconnect

Granted: September 6, 2011
Patent Number: 8015330
In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first…

Selection of filter coefficients for tranceiver non-linearity signal cancellation

Granted: June 7, 2011
Patent Number: 7957456
Embodiments of a method and apparatus for selecting coefficients of a non-linear filter are disclosed. The non-linear filter receives a transmit signal and generates a non-linear replica signal of a transmit DAC of a transceiver. The method include applying a plurality of periodic test pattern signals to inputs of the transmit DAC, wherein the periodic test pattern signals include a stream of symbols. Receive symbols are collected at an output of a receiver ADC of the transceiver…

Controlling activation of electronic circuitry of data ports of a communication system

Granted: February 1, 2011
Patent Number: 7881330
An apparatus and method of controlling activation of electronic circuitry of data ports of a communication system is disclosed. One method includes a first data port detecting a lack of data for transmission to a second data port. At least one of the first data port and a second data port deactivate electronic circuitry of at least one of the first and second data ports upon detection of the lack of data. The first and second data ports maintain synchronization with each other while the…

Dynamic buffer pool in PCIExpress switches

Granted: January 11, 2011
Patent Number: 7869356
In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the…

Master/slave transceiver power back-off

Granted: December 28, 2010
Patent Number: 7860020
An apparatus and method of setting power back-off of a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

Circuit for voltage controlled oscillator

Granted: November 16, 2010
Patent Number: 7834709
A voltage controlled oscillator and a load cell circuit usable in VCO are provided. The VCO features an internal compensation for process, voltage and temperature using a replica of half of the oscillating stage. The load cell circuit comprises a bias transistor to drain a predetermined current from the oscillating stage, a control transistor to vary resistance offered by it responsive to a control voltage applied and a resistor adapted to provide a clamp resistance.

Random number generation

Granted: February 9, 2010
Patent Number: 7660944
A controller for controlling the operation of a hard disk drive is capable of generating a random number using the hard disk drive. Initially the hard disk drive is disabled from performing a read-ahead operation. Random addresses on the hard disk drive are generated from the output of the pseudo-random number generator. Read-verify commands is sent to the hard disk drive to perform a read-verify operation of reading and verifying the data stored in the sectors of the hard disk drive at…

Virtual endpoint for USB devices

Granted: May 22, 2007
Patent Number: 7222201
In a USB device, virtual endpoint capability allows a number of physical endpoints in the device to support a larger number of data pipes at logical endpoints requested by the host. This is done by re-assigning physical endpoints to support the logical endpoint requested by the host. The logical endpoints and their corresponding data pipes may be served in a round robin scheme.

On-chip switch fabric

Granted: May 2, 2006
Patent Number: 7039750
A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates…

Method and apparatus for fault tolerant, software transparent and high data integrity extension to a backplane or bus interconnect

Granted: April 26, 2005
Patent Number: 6885670
The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells…

Method, system and apparatus for a computer subsystem interconnection using a chain of bus repeaters

Granted: February 1, 2005
Patent Number: 6851009
The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell…

Method, system and apparatus for a computer subsystem interconnection using a chain of bus repeaters

Granted: June 17, 2003
Patent Number: 6581126
The invention discloses methods and apparatus for broadcasting information across an interconnect that includes a plurality of nodes each connected to its adjacent node(s) using one or more links. The nodes can emit cells containing transaction sub-actions onto the links. As a node receives a cell the node retransmits the cell onto other links as the cell is being received. Thus, reducing the latency imposed by the node. The node also captures the transaction sub-action while it the cell…

Method and apparatus for a fault tolerant, software transparent and high data integrity extension to a backplane bus or interconnect

Granted: June 4, 2002
Patent Number: 6400682
The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells…

Method and apparatus for a fault tolerant software transparent and high data integrity extension to a backplane bus or interconnect

Granted: April 3, 2001
Patent Number: 6212161
The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells…

Binary relative delay line

Granted: September 9, 1997
Patent Number: 5666079
A binary relative delay line device having two delay lines, each of which delays, during a time interval, an input signal by a substantially equal amount of time. Each delay line requires a settling time before it is selected during a next time interval. A selection and delay determining circuit is coupled to the two delay lines to select one of them to provide an output signal. A clock is coupled to the selection and delay determining circuit to operate the selection and delay…