Pulse Output Direct Digital Synthesis Circuit
Granted: November 29, 2007
Application Number:
20070276891
A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency fref. The clock signal generator generates an output clock signal having a frequency fgen, wherein fgen is less than fref. A modulo-N counter accepts the reference clock signal as input. The modulo-N counter generates a phase-indication signal of the reference clock. The phase indication signal has N clock phases repeating at a frequency of fref/N. An…
METHOD AND SYSTEM FOR PASSIVE OPTICAL NETWORK DIAGNOSTICS
Granted: June 21, 2007
Application Number:
20070140689
A method and system for identifying faults in a passive optical network (PON), The method comprises acquiring at an optical network terminal of the PON at least one parameter indicative of at least one malfunction in at least one optical network unit of the PON, and identifying each malfunction from the at least one parameter The parameters measured include, for each ONU, laser power, sync-lock and -unlock time and bit error rates. The information at the OLT is acquired remotely and in…
Method and apparatus for detection of high-speed electrical signals
Granted: November 16, 2006
Application Number:
20060255860
A signal detector includes, in part, first and second peak detectors, a comparator and an amplifier. The first peak detector generates a first signal in response to receiving an incoming signal. The second peak detector generates a second signal in response to receiving a threshold signal. The comparator generates an output signal representing the detected signal in response to the first and second signals. The amplifier amplifies the difference between the second signal and a reference…
ON-CHIP INTER-SUBSYSTEM COMMUNICATION INCLUDING CONCURRENT DATA TRAFFIC ROUTING
Granted: October 5, 2006
Application Number:
20060221931
In an integrated circuit, a data traffic router includes a number of multiplexors coupled to each other, and to subsystems of the IC. The subsystems selectively output to each other. The data traffic router selectively provides paths for the outputs to reach their destinations, to facilitate concurrent communications between at least two selected combinations of the subsystems.
Virtual concatenation of PDH signals
Granted: October 5, 2006
Application Number:
20060222005
Asynchronous/plesiochronous digital hierarchy (PDH) signals, such as DS1 and E1, are transported using virtual concatenation. The packetized data signals are frame encapsulated and subsequently inverse multiplexed into a plurality of PDH frames. An overhead packet is inserted in the transmitted frames to enable the receiver to determine the status of the frames and extract the differential delay experienced by various frames as they are routed through virtually concatenated channels. The…
FEEDBACK PRIORITY MODULATION RATE CONTROLLER
Granted: September 21, 2006
Application Number:
20060209693
Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority…
DMA engine for protocol processing
Granted: September 14, 2006
Application Number:
20060206635
A DMA engine, includes, in part, a DMA controller, an associative memory buffer, a request FIFO accepting data transfer requests from a programmable engine, such as a CPU, and a response FIFO that returns the completion status of the transfer requests to the CPU. Each request includes, in part, a target external memory address from which data is to be loaded or to which data is to be stored; a block size, specifying the amount of data to be transferred; and context information. The…
Serial data validity monitor
Granted: February 3, 2005
Application Number:
20050025195
A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance monitor is configured to detect DC imbalances in the incoming data and that may be indicative of errors in the data. The transition density detector is configured to detect whether a minimum transition density exists during a…
Method and apparatus for interconnection offlow-controlled communication
Granted: December 23, 2004
Application Number:
20040257997
A method or system or apparatus provides improved digital communication. In one aspect, flow control in performed by receiving status preprended to data units in a combined data channel, where the status data indicated the available status of a number of far end receiving channels. Thus data may be sent only to available receiving channels. In a further aspect, a frequency reference may also be transmitted by including data in data units in a combined channel. In a further aspect, an…
Differential delay compensation
Granted: May 22, 2003
Application Number:
20030095563
An alignment logic together with an MFI extractor are adapted to compensate for differential delays. The MFI extractor extracts the MFI disposed in the path overhead of each constituent time-slot. The alignment logic uses the extracted MFI to align corresponding data words (i.e., data words that are transmitted during the same time period) at the receiving end of virtually concatenated channels and that occupy different time-slots of the same channel. To perform alignment, the alignment…
Transmit virtual concatenation processor
Granted: March 6, 2003
Application Number:
20030043851
A transmit virtual concatenation processor for multiplexing channelized data onto a SONET/SDH frame is disclosed. The processor is scalable and is able to handle mapping a number of data channels to a number of different frame sizes including STS-12, STS-48, STS-192 and STS-768. The processor supports virtual concatenation with arbitrary channel mapping at both STS-1 and STS-3c granularities. The processor also supports contiguous concatenation with STS-12c, STS-24c, STS-48c, STS-192c,…
Subtraction in a viterbi decoder
Granted: August 22, 2002
Application Number:
20020116682
A Viterbi decoder for decoding a convolutional code. For each possible state, an accumulated error AE is maintained at 66. As each codeword Rx-GP is received, the errors between it and the code groups of all the transitions are determined at 65. For each possible new state, logic 68 determines the errors of the two transitions leading from old states to that new state, adds them to the accumulated errors of those two old states, and determines the smaller of the two sums. Path logic 67…
Minimum error detection in a viterbi decoder
Granted: August 15, 2002
Application Number:
20020112211
A Viterbi decoder for decoding a convolutional code. For each possible state, an accumulated error AE is maintained at 66. As each codeword Rx-GP is received, the errors between it and the code groups of all the transitions are determined at 65. For each possible new state, logic 68 determines the errors of the two transitions leading from old states to that new state, adds them the accumulated errors of those two old states, and determines the smaller of the two sums. Path logic 67…
Multi-channel SONET/SDH desynchronizer
Granted: February 21, 2002
Application Number:
20020021719
A desynchronizer for desynchronizing one or multiple channels of SONET/SDH data signals, which includes a first in first out (FIFO) buffer having an input coupled to said data signals and an output for outputting asynchronous data obtained from one or more of said SONET/SDH data channels. An arithmetic unit coupled to the FIFO performs all operations required for single or multi-channel desynchronization. An endless phase modulator is coupled to the arithmetic unit and to the FIFO and is…
