PMC-Sierra Patent Grants

Low-noise flexible frequency clock generation from two fixed-frequency references

Granted: December 15, 2015
Patent Number: 9215062
A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output…

Systems and methods for reclaiming memory for solid-state memory

Granted: December 8, 2015
Patent Number: 9208018
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Apparatus and method for modulating a laser beam and sensing the optical power thereof

Granted: November 24, 2015
Patent Number: 9197318
A method and apparatus for modulating a beam from a laser with an electro-absorption modulator, and determining the optical power of the beam by measuring a back current produced by the electro-absorption modulator. The apparatus comprises an electro-absorption modulator and a back current detector. The electro-absorption modulator receives an electronic digital signal from an electro-absorption driver. The electro-absorption modulator modulates the beam of the laser according to the…

Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency

Granted: November 10, 2015
Patent Number: 9183085
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Predefined gears correspond to different predefined ECC schemes. Based on an observed bit error rate, a gear from a set of predefined gears is selected for use for a particular region of…

Systems and methods for storing data in page stripes of a flash drive

Granted: November 3, 2015
Patent Number: 9176812
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Data is stored in page stripes. The page stripes can have varying amounts of payload capacity based on selected error correction code strength. Allocation blocks can be divided into…

Method and system for decoding encoded data stored in a non-volatile memory

Granted: October 27, 2015
Patent Number: 9170876
A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of…

Reed-solomon decoder

Granted: October 20, 2015
Patent Number: 9166623
A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The…

Link selection in a bonding protocol

Granted: October 13, 2015
Patent Number: 9160673
A method is provided for selecting a transmit link in a bonding group. Traffic is distributed to the links based on a selection method. Typical selection methods for bonded links of the same type include round robin or weighted round robin. A method is disclosed including selecting from among bonded links of different types based on link priority or link-to-group backpressure, sometimes both, and in some cases also based on traffic class. Link priority is based on the reliability, or…

Scalable high-swing transmitter with rise and/or fall time mismatch compensation

Granted: September 29, 2015
Patent Number: 9148146
Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations…

Method for reducing jitter in receivers

Granted: September 22, 2015
Patent Number: 9143371
A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.

Transformer based circuit for reducing EMI radiation in high speed CMOS SERDES transmitters

Granted: September 8, 2015
Patent Number: 9130650
This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a post-cursor branch comprising a delay, an inverter and a series terminating resistance connected between the first input and a first circuit arm common node, and a main cursor branch comprising a buffer and a series terminating resistance…

Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values

Granted: September 8, 2015
Patent Number: 9128858
Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder…

Scrambler with built in test capabilities for unary DAC

Granted: September 1, 2015
Patent Number: 9124287
An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage…

Reflective analog finite impulse response filter

Granted: August 25, 2015
Patent Number: 9118511
A distributed Analog Finite Impulse Response (AFIR) filter circuit with n physical taps provides an output equivalent to an AFIR filter circuit with 2n?1 taps by emulating n?1 taps. An impedance mismatch, with respect to the characteristic impedance of the input and output transmission lines, is imposed at the input and output terminals to take advantage of the resulting reflective signal paths, which emulate the additional taps. This implementation results in space-savings and…

Low-noise flexible frequency clock generation from two fixed-frequency references

Granted: August 18, 2015
Patent Number: 9112517
A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output…

Method of reducing current leakage in a product variant of a semiconductor device

Granted: August 11, 2015
Patent Number: 9104825
A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that…

Quantization noise-shaping device

Granted: July 28, 2015
Patent Number: 9094033
A device that performs Quantization Noise-Shaping and operates at high clock rates. The device can be implemented in parallel with large parallelization factors to produce extremely high throughput. The device has two feed-forward filters that can be implemented using standard parallel Digital Signal Processing techniques. The device can be used in various systems such as Digital-to-Analog Converter (DAC) system and Fractional-N frequency synthesis systems.

Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

Granted: July 28, 2015
Patent Number: 9092353
Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated…

Wide-range fast-lock frequency acquisition for clock and data recovery

Granted: July 28, 2015
Patent Number: 9091711
A method and system are disclosed which determine a frequency offset between a reference clock frequency of a receiver and a transmit clock frequency embedded in a received non-return to zero (NRZ) signal. A polarity of the frequency offset is determined based on a moving direction of a sampling clock edge relative to an edge of a signal eye of the received NRZ signal and a region of the signal eye containing the sampling clock edge. A magnitude of the frequency offset is determined…

Voltage controlled oscillator with common mode adjustment start-up

Granted: July 14, 2015
Patent Number: 9083349
The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.