Signal Distribution Networks and Related Methods
Granted: November 13, 2014
Application Number:
20140333356
A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal…
PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM
Granted: November 6, 2014
Application Number:
20140329359
Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first…
DISTRIBUTED SUB-PAGE SELECTION
Granted: October 9, 2014
Application Number:
20140301151
Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead.
Data Transmission Using Delayed Timing Signals
Granted: October 2, 2014
Application Number:
20140293710
An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external…
Configurable Width Memory Modules
Granted: October 2, 2014
Application Number:
20140293671
Describes is a memory system that utilizes motherboard traces in a way that permits maximum utilization of system data lines while accommodating varying numbers of memory modules. It is possible in a system such as this to utilize all individual sets of point-to-point signaling lines, even when less than all of the available memory sockets are occupied. Memory modules with configurable data widths support a relatively wide mode in which one module utilizes all available system data…
MULTI-ANTENNA TRANSMITTER FOR MULTI-TONE SIGNALING
Granted: September 25, 2014
Application Number:
20140286450
Embodiments of a communication circuit are described. This communication circuit includes an input node to receive a set of data symbols and a partitioner coupled to the input node. This partitioner is to divide the set of data symbols into M irregular subgroups of data symbols, a given one of which includes non-consecutive data symbols in the set of data symbols. Moreover, this given irregular subgroup of data symbols includes at least two pairs of adjacent data symbols having different…
Multiphase Receiver with Equalization Circuitry
Granted: September 25, 2014
Application Number:
20140286389
An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to…
Selectable-tap Equalizer
Granted: September 25, 2014
Application Number:
20140286383
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of…
Methods and Systems for Reducing Supply and Termination Noise
Granted: September 25, 2014
Application Number:
20140285232
Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.
MEMORY CIRCUIT AND METHOD FOR ITS OPERATION
Granted: September 18, 2014
Application Number:
20140281205
In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating…
LASER MICROMACHINING OPTICAL ELEMENTS IN A SUBSTRATE
Granted: September 18, 2014
Application Number:
20140272329
Optical elements with small increments in average density are formed in a substrate by laser micromachining using a variable aperture and a pattern mask set of pattern masks each having of shape-defining elements whose density differs among the pattern masks in first density increments. A laser light beam passes through a combined mask formed by the variable aperture and one pattern mask selected from the pattern mask set. The variable aperture controls beam size and the pattern mask…
FAST READ SPEED MEMORY DEVICE
Granted: September 18, 2014
Application Number:
20140269006
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node.
Memory Controller Supporting Nonvolatile Physical Memory
Granted: September 11, 2014
Application Number:
20140258601
A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS
Granted: September 11, 2014
Application Number:
20140254294
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using…
THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT
Granted: September 11, 2014
Application Number:
20140254286
In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range.
Phase Gratings with Odd Symmetry for High-Resolution Lensed and Lensless Optical Sensing
Granted: September 11, 2014
Application Number:
20140253781
A sensing device with an odd-symmetry grating projects near-field spatial modulations onto a closely spaced photodetector array. Due to physical properties of the grating, the spatial modulations are in focus for a range of wavelengths and spacings. The spatial modulations are captured by the array, and photographs and other image information can be extracted from the resultant data. Used in conjunction with a converging optical element, versions of these gratings provide depth…
OPEN-LOOP CORRECTION OF DUTY-CYCLE ERROR AND QUADRATURE PHASE ERROR
Granted: September 11, 2014
Application Number:
20140253195
A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various…
MULTI-DIE MEMORY DEVICE
Granted: September 4, 2014
Application Number:
20140247637
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array…
PROGRAMMABLE MEMORY REPAIR SCHEME
Granted: September 4, 2014
Application Number:
20140247678
A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the…
Pulse Control For NonVolatile Memory
Granted: September 4, 2014
Application Number:
20140247656
A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because…
