Rambus Patent Grants

Expandable asymmetric-channel memory system

Granted: April 25, 2017
Patent Number: 9632956
An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Light emitting panel assemblies

Granted: April 18, 2017
Patent Number: 9625633
An optical assembly comprises light sources and a light emitting panel member having an input edge to which each of the light sources is optically coupled at a different location along the input edge. Different sets of individual optical deformities on or in at least one of the sides of the panel member each have at least one surface that is shaped or oriented to extract light propagating in the same direction through the panel member in different directions for viewing from different…

Communication channel calibration for drift conditions

Granted: April 18, 2017
Patent Number: 9628257
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…

Memory controller system with non-volatile backup storage

Granted: February 21, 2017
Patent Number: 9575686
The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the…

Error correction in a memory device

Granted: February 21, 2017
Patent Number: 9575835
A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the…

Clock and data recovery having shared clock generator

Granted: February 21, 2017
Patent Number: 9577816
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay…

Testing fuse configurations in semiconductor devices

Granted: February 14, 2017
Patent Number: 9568544
A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically…

Delay fault testing for chip I/O

Granted: February 14, 2017
Patent Number: 9568546
An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first…

Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency

Granted: February 14, 2017
Patent Number: 9568942
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device…

Using dynamic bursts to support frequency-agile memory interfaces

Granted: February 14, 2017
Patent Number: 9568980
The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts…

Reduced-overhead error detection and correction

Granted: February 14, 2017
Patent Number: 9569308
A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.

Methods and apparatuses for addressing memory caches

Granted: February 14, 2017
Patent Number: 9569359
A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective…

Memory module threading with staggered data transfers

Granted: February 14, 2017
Patent Number: 9569393
A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data…

Interface with variable data rate

Granted: February 14, 2017
Patent Number: 9569396
A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Memory with deferred fractional row activation

Granted: February 14, 2017
Patent Number: 9570126
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Resistance change memory cell circuits and methods

Granted: February 14, 2017
Patent Number: 9570171
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially…

Testing through-silicon-vias

Granted: February 14, 2017
Patent Number: 9570196
Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and…

Electronic circuits using coupled multi-inductors

Granted: February 14, 2017
Patent Number: 9571034
Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase…

Dynamic update technique for phase interpolator device and method therefor

Granted: February 14, 2017
Patent Number: 9571077
A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out…

In-band status encoding and decoding using error correction symbols

Granted: February 14, 2017
Patent Number: 9571231
A status encoder generates a checksum that encodes a status condition together with the checksum of an associated message. A receiver determines an inverse transformation that when applied to the received status-encoded checksum recovers the parity information associated with the codeword. The status condition can then be recovered based on the selection of the inverse transformation that correctly recovers the parity information from the status-encoded checksum. Beneficially, the status…