Rambus Patent Grants

Single command, multiple column-operation memory device

Granted: May 23, 2017
Patent Number: 9658953
A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the…

Controller to detect malfunctioning address of memory device

Granted: May 23, 2017
Patent Number: 9659671
A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate…

On-die termination control

Granted: May 23, 2017
Patent Number: 9660648
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received.…

Selectable-tap equalizer

Granted: May 23, 2017
Patent Number: 9660840
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of…

Decision feedback equalizer

Granted: May 23, 2017
Patent Number: 9660844
A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to…

Equalized multi-signaling mode driver

Granted: May 23, 2017
Patent Number: 9660847
A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap is repurposed to generate, along with the main tap, the main PAM-4 signaling levels. At least one PAM-2 FFE tap is repurposed to apply FFE in the PAM-4 mode.

Memory controller for micro-threaded memory operations

Granted: May 16, 2017
Patent Number: 9652176
A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount…

Memory access during memory calibration

Granted: May 16, 2017
Patent Number: 9652409
A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also…

High capacity memory system using standard controller component

Granted: May 16, 2017
Patent Number: 9653146
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Lighting assembly with edge-lit light guide and structured cover

Granted: May 9, 2017
Patent Number: 9645301
A cover element for use in a lighting assembly that includes an edge-lit light guide. The cover element includes a first major surface through which light output by the light guide enters the cover element, the light including light propagating at high angles relative to normal to the first major surface of the cover element. The cover element also includes a second major surface opposed to the first major surface and having optical elements that each have plural surfaces arranged…

Optimizing power in a memory device

Granted: May 9, 2017
Patent Number: 9645631
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at…

Article of manufacture with micro-features of differing surface roughness

Granted: May 2, 2017
Patent Number: 9638853
An article of manufacture includes first and second micro-features of well-defined shape. In some embodiments, the article of manufacture is a light guide or redirecting film and the second micro-features are micro-optical elements configured to disrupt a specular optical path that includes the second micro-optical element. In other embodiments, the article of manufacture is a patterning tool for use in making an optical substrate. Embodiments of the optical substrate are formed by…

Expandable asymmetric-channel memory system

Granted: April 25, 2017
Patent Number: 9632956
An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Light emitting panel assemblies

Granted: April 18, 2017
Patent Number: 9625633
An optical assembly comprises light sources and a light emitting panel member having an input edge to which each of the light sources is optically coupled at a different location along the input edge. Different sets of individual optical deformities on or in at least one of the sides of the panel member each have at least one surface that is shaped or oriented to extract light propagating in the same direction through the panel member in different directions for viewing from different…

Communication channel calibration for drift conditions

Granted: April 18, 2017
Patent Number: 9628257
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…

Memory controller system with non-volatile backup storage

Granted: February 21, 2017
Patent Number: 9575686
The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the…

Error correction in a memory device

Granted: February 21, 2017
Patent Number: 9575835
A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the…

Clock and data recovery having shared clock generator

Granted: February 21, 2017
Patent Number: 9577816
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay…

Testing fuse configurations in semiconductor devices

Granted: February 14, 2017
Patent Number: 9568544
A system includes a first integrated circuit configured to operate in at least a normal mode and a test mode and a second integrated circuit, where both the first integrated circuit and the second integrated circuit are disposed within a same semiconductor device package. The system further includes a first terminal, external to the semiconductor device package, electronically coupled to the first integrated circuit and the second integrated circuit. The first terminal is electronically…

Resistance change memory cell circuits and methods

Granted: February 14, 2017
Patent Number: 9570171
The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially…