Rambus Patent Grants

Laser micromachining optical elements in a substrate

Granted: July 18, 2017
Patent Number: 9707641
Optical elements with small increments in average density are formed in a substrate by laser micromachining using a variable aperture and a pattern mask set of pattern masks each having of shape-defining elements whose density differs among the pattern masks in first density increments. A laser light beam passes through a combined mask formed by the variable aperture and one pattern mask selected from the pattern mask set. The variable aperture controls beam size and the pattern mask…

Drift tracking feedback for communication channels

Granted: July 18, 2017
Patent Number: 9710011
A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of…

Unsuccessful write retry buffer

Granted: July 18, 2017
Patent Number: 9710226
A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the…

Data independent periodic calibration using per-pin VREF correction technique for single-ended signaling

Granted: July 18, 2017
Patent Number: 9711239
A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a…

System and method for memory access in server communications

Granted: July 18, 2017
Patent Number: 9712373
Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server that has memory management module that is connected to the processor using one or more DDR channels. The memory management module is configured to provide the processor local access and network access to memories on a network. There are other embodiments as well.

Extrusion-to-sheet production line and method

Granted: July 11, 2017
Patent Number: 9701060
Extrusion-to-sheet production line and method comprise first and second rolls set to a predetermined gap through which a continuously-extruded sheet of molten plastic material passes to calender the sheet to a predetermined thickness. The sheet passes through a nip formed between the second roll and a continuous belt looped around a third roll and a fourth roll. The belt comprises an embossing pattern of optical element shapes that is an inverse pattern of optical element shapes to be…

Light guide and lighting assembly with array of rotated micro-optical elements

Granted: July 11, 2017
Patent Number: 9703031
A light guide includes opposed major surfaces and a light input edge extending therebetween. An array of micro-optical elements of well-defined shape at at least one of the opposed major surfaces corresponds to the light input edge. Each of the micro-optical elements in the array includes a longitudinal axis arranged within the range of angles relative to the light input edge. A path linearly extending along the light guide from the light input edge intersects at least a portion of the…

Multiple memory rank system and selection method thereof

Granted: July 11, 2017
Patent Number: 9703483
A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first…

Reconfigurable memory system data strobes

Granted: July 11, 2017
Patent Number: 9703503
In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the…

Memory component with staggered power-down exit

Granted: July 11, 2017
Patent Number: 9704560
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Complementary RRAM applications for logic and ternary content addressable memory (TCAM)

Granted: July 11, 2017
Patent Number: 9704576
A ternary content addressable memory (TCAM) cell may include a first resistive memory element, a second resistive memory element, a third resistive memory element, and a first switching element. The first resistive memory element may be disposed between a true data bit line node and a common node. The second resistive memory element may be disposed between a complement data bit line node and the common node. The third resistive element may be coupled to the common node and a word line…

On-die termination

Granted: July 11, 2017
Patent Number: 9705498
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

High speed signaling system with adaptive transmit pre-emphasis

Granted: July 11, 2017
Patent Number: 9705710
A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to…

Variable width memory module supporting enhanced error detection and correction

Granted: July 4, 2017
Patent Number: 9697884
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Variable code rate transmission

Granted: July 4, 2017
Patent Number: 9698935
An integrated circuit device includes an output buffer circuit that provides a first output having a first code rate. The first output is provided in response to a first indication of a change in a parameter that affects an error rate of the first output. The first output includes redundant information. The output buffer circuit provides a second output having a second code rate. The second output is provided in response to a second indication of the second output having an error rate…

Memory controller with staggered request signal output

Granted: June 27, 2017
Patent Number: 9691447
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Memory controller with phase adjusted clock for performing memory operations

Granted: June 27, 2017
Patent Number: 9691454
In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating…

DRAM retention test method for dynamic error correction

Granted: June 27, 2017
Patent Number: 9691504
A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Wide range frequency synthesizer with quadrature generation and spur cancellation

Granted: June 27, 2017
Patent Number: 9692431
A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The…

On-chip regulator with variable load compensation

Granted: June 20, 2017
Patent Number: 9684321
An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.