Rambus Patent Grants

Multi-die DRAM banks arrangement and wiring

Granted: January 17, 2017
Patent Number: 9548102
The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory die with a plurality of memory banks and a plurality of contacts. The method includes: (1) coupling a first memory bank of the plurality of memory banks to a second memory die via the plurality of contacts; (2) transmitting data between the first memory bank and the second memory die via the plurality of contacts; and (3) receiving…

Margin test methods and circuits

Granted: January 10, 2017
Patent Number: 9544071
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device…

Multiphase receiver with equalization circuitry

Granted: January 10, 2017
Patent Number: 9544169
An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to…

Methods and circuits for adaptive equalization

Granted: January 10, 2017
Patent Number: 9544170
An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

Low-power source-synchronous signaling

Granted: January 3, 2017
Patent Number: 9536589
A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated…

Phase interpolator device using dynamic stop and phase code update and method therefor

Granted: January 3, 2017
Patent Number: 9537475
A method and device for dynamically updating a phase interpolator circuit module using an update control circuit module. The method can include providing the phase interpolator with a set of input clock phases to produce a clock signal. The update control module can generate a blanking signal in response to an update signal and apply an update process that stops an old clock output signal after a last clock pulse. The update control module can then update phase select multiplexers for a…

Receiver clock test circuitry and related methods and apparatuses

Granted: January 3, 2017
Patent Number: 9537617
An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data…

Frequency-agile clock multiplier

Granted: December 27, 2016
Patent Number: 9531391
Upon detecting transition of an input timing signal from a non-oscillating state to an oscillating state, a clock generating circuit is switched from a paused mode to an open-loop operating mode to transition an output timing signal of the clock generating circuit from a non-oscillating state to an oscillating state in which the output timing signal oscillates at a free-running frequency. A ratio of a reference frequency of the oscillating-state input timing signal and the free-running…

Reset-marking pixel sensor

Granted: December 13, 2016
Patent Number: 9521337
A self-resetting pixel having a memory element to record occurrence of an asynchronous pixel reset and circuitry to enable the memory element to be digitally sampled and cleared is disclosed, together with embodiments of digital image sensors formed by arrays or other collections of such pixels. By marking occurrence of asynchronous reset events within an in-pixel memory element that may be digitally oversampled during an exposure interval (i.e., repeatedly read-out in the form of, for…

Image sensor sampled at non-uniform intervals

Granted: December 13, 2016
Patent Number: 9521338
In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.

Image sensor architecture with power saving readout

Granted: December 13, 2016
Patent Number: 9521349
Pixels within an image sensor pixel array are sampled by corresponding conditional read circuitry. A zero pixel value is outputted for each pixel associated with a sample less than a conversion threshold, and a saturated pixel value is outputted for each pixel associated with a sample greater than or equal to a saturation threshold. Samples greater than or equal to the conversion threshold and less than the saturation threshold are converted by an ADC, and a converted pixel value is…

Fractional-readout oversampled image sensor

Granted: December 13, 2016
Patent Number: 9521351
Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of…

Lighting assembly

Granted: December 6, 2016
Patent Number: 9513428
A lighting assembly includes a light engine and a light guide. The light engine edge lights the light guide and includes a control assembly that controls light output according to one or more parameters to produce light output from the lighting assembly with a desired characteristic. Lighting assemblies are combined to form a modular lighting assembly.

Strobe gating adaption and training in a memory controller

Granted: December 6, 2016
Patent Number: 9514420
A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the…

Techniques for interconnecting stacked dies using connection sites

Granted: December 6, 2016
Patent Number: 9515008
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.

Optical sensing of nearby scenes with tessellated phase anti-symmetric gratings

Granted: December 6, 2016
Patent Number: 9515113
An array of diffraction-pattern generators employ phase anti-symmetric gratings to projects near-field spatial modulations onto a closely spaced array of photoelements. Each generator in the array of generators produces point-spread functions with spatial frequencies and orientations of interest. The generators are arranged in an irregular mosaic with little or no short-range repetition. Diverse generators are shaped and placed with some irregularity to reduce or eliminate spatially…

Synchronous wired-or ACK status for memory with variable write latency

Granted: December 6, 2016
Patent Number: 9515204
A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the…

Phase control block for managing multiple clock domains in systems with frequency offsets

Granted: December 6, 2016
Patent Number: 9515814
A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase…

Offset and decision feedback equalization calibration

Granted: December 6, 2016
Patent Number: 9515856
A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the…

Virtualized cache memory

Granted: November 29, 2016
Patent Number: 9507731
A memory address and a virtual cache identifier are received in association with a request to retrieve data from a cache data array. Context information is selected based on the virtual cache identifier, the context information indicating a first region of a plurality of regions within the cache data array. A cache line address that includes a first number of bits of the memory address in accordance with a size of the first region is generated and, if the cache data array is determined…