Sandisk Patent Applications

SYSTEM AND METHOD FOR MEMORY INTEGRATED CIRCUIT CHIP WRITE ABORT INDICATION

Granted: August 17, 2017
Application Number: 20170236590
Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being…

IMPLEMENTATION OF VMCO AREA SWITCHING CELL TO VBL ARCHITECTURE

Granted: August 17, 2017
Application Number: 20170236871
Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of…

WORDLINE SIDEWALL RECESS FOR INTEGRATING PLANAR SELECTOR DEVICE

Granted: August 17, 2017
Application Number: 20170236873
Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the…

Memory System and Method for Simplifying Scheduling on a Flash Interface Module and Reducing Latencies in a Multi-Die Environment

Granted: August 10, 2017
Application Number: 20170228167
A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die…

SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY

Granted: August 10, 2017
Application Number: 20170229339
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

END OF LIFE PREDICTION BASED ON MEMORY WEAR

Granted: August 3, 2017
Application Number: 20170221573
A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear,…

SYSTEMS AND METHODS FOR IMMEDIATE PHYSICAL ERASURE OF DATA STORED IN A MEMORY SYSTEM IN RESPONSE TO A USER COMMAND

Granted: July 27, 2017
Application Number: 20170212833
Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further…

ESD CENTRIC LOW-COST IO LAYOUT DESIGN TOPOLOGY

Granted: July 27, 2017
Application Number: 20170213817
An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more…

NON-VOLATILE MEMORY HAVING INDIVIDUALLY OPTIMIZED SILICIDE CONTACTS AND PROCESS THEREFOR

Granted: July 20, 2017
Application Number: 20170207092
In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication…

FAST SETTLING LOW DROPOUT VOLTAGE REGULATOR

Granted: July 13, 2017
Application Number: 20170199536
Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a…

DATA PATH CONTROL FOR NON-VOLATILE MEMORY

Granted: July 13, 2017
Application Number: 20170199668
Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations.…

PHYSICAL ADDRESSING SCHEMES FOR NON-VOLATILE MEMORY SYSTEMS EMPLOYING MULTI-DIE INTERLEAVE SCHEMES

Granted: July 13, 2017
Application Number: 20170199703
A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows…

NON-VOLATILE MEMORY WITH EFFICIENT PROGRAMMING

Granted: July 13, 2017
Application Number: 20170200501
A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select…

Memory System and Method for Power Management for Reducing a Variable Credit Value By a Computed Consumed Energy Value for Each Corresponding Updated Cycle

Granted: July 6, 2017
Application Number: 20170192722
In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time…

Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization

Granted: June 29, 2017
Application Number: 20170185299
A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by…

PARITY STORAGE MANAGEMENT

Granted: June 29, 2017
Application Number: 20170185472
Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.

KEY-VALUE STORE WITH PARTIAL DATA ACCESS

Granted: June 29, 2017
Application Number: 20170185625
Apparatuses, systems, methods, and computer program products are disclosed for key-value stores with partial data access. An interface module is configured to receive a data object for storage in a key-value store. The data object may include a key and a value. A block object module is configured to generate a plurality of block objects smaller than the data object. A block object may include a new key and a new value. The new key may be based on the key for the data object and on…

SOLID STATE DRIVE OPTIMIZED FOR WAFERS

Granted: June 29, 2017
Application Number: 20170186731
An SSD with a package optimized for semiconductor wafers is configured by thinning a plurality of undiced wafers and stacking the wafers. The wafers are connected to each other by TSV. A subset of the wafers include memory circuits. One of the wafer not in the subset includes peripheral circuits. A casing houses the wafers.

SUB-BLOCK MODE FOR NON-VOLATILE MEMORY

Granted: June 22, 2017
Application Number: 20170178736
Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one…

BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE

Granted: June 22, 2017
Application Number: 20170179101
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an…