Sandisk Patent Applications

Memory System and Method for Improving Write Performance in a Multi-Die Environment

Granted: May 18, 2017
Application Number: 20170139590
A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are…

State Dependent Sensing For Wordline Interference Correction

Granted: May 18, 2017
Application Number: 20170140814
A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower…

MEMORY CELLS INCLUDING VERTICALLY ORIENTED ADJUSTABLE RESISTANCE STRUCTURES

Granted: May 18, 2017
Application Number: 20170141304
A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

MULTI-PROCESSOR NON-VOLATILE MEMORY SYSTEM HAVING A LOCKLESS FLOW DATA PATH

Granted: May 4, 2017
Application Number: 20170123696
A system and method is disclosed for managing a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors and a shared data queue in a cyclic data buffer. Each of the plurality of processors may manage a separate pointer pointing to a different entry of the shared data queue and multiple ones of the processors may concurrently access or update entries in the shared data queue.

SYSTEM AND METHOD FOR UTILIZATION OF A DATA BUFFER BY COMMAND COMPLETION IN PARTS

Granted: May 4, 2017
Application Number: 20170123721
Systems and methods for managing transfer of data into and out of a host data buffer of a host are disclosed. In one implementation, a partial write completion module of a storage system retrieves from the host, stores in a memory, and acknowledges retrieving and storing with a partial write completion message, each subset of a larger set of data associated with a host write command. The host may utilize received partial write completion messages to release and use the portion of the…

SYSTEM AND METHOD FOR UTILIZATION OF A DATA BUFFER

Granted: May 4, 2017
Application Number: 20170123722
Systems and methods for managing transfer of data into and out of a host data buffer of a host are disclosed. In one implementation, a partial write completion module of a storage system retrieves from the host, stores in a memory, and acknowledges retrieving and storing with a partial write completion message, each subset of a larger set of data associated with a host write command. The host may utilize received partial write completion messages to release and use the portion of the…

SYSTEM AND METHOD FOR UTILIZATION OF A DATA BUFFER IN A STORAGE DEVICE

Granted: May 4, 2017
Application Number: 20170123991
Systems and methods for managing a data buffer of a non-volatile memory system are disclosed. The method may include a controller of a storage system retrieving host data, storing the retrieved data in a data buffer and transferring the data to a non-volatile memory. The controller may then overwrite the retrieved data in the data buffer as soon as the retrieved data has been transferred to the non-volatile memory die but prior to sending a command to program that data to the…

Handling Of Plane Failure In Non-Volatile Storage

Granted: May 4, 2017
Application Number: 20170123994
Technology is described herein for reclaiming a memory device that has a defective plane. A solution allows a memory device with a defective plane to operate as a single plane device. The memory device with the defective plane may be used without any changes to the memory controller. Thus, the memory controller can send single plane commands to the memory device with the defective plane by using single plane addressing. The memory device may have logic that properly translates the single…

DYNAMIC THRESHOLD VOLTAGE COMPACTION FOR NON-VOLATILE MEMORY

Granted: May 4, 2017
Application Number: 20170125087
Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.

PROGRAM SEQUENCING

Granted: May 4, 2017
Application Number: 20170125101
Apparatuses, systems, methods, and computer program products are disclosed for program sequencing. An apparatus includes a block of non-volatile storage cells having a plurality of word lines. The word lines are organized into a monotonically increasing sequence. The apparatus includes a controller for the block. The controller is configured to program a set of storage cells of a word line to one or more storage states above a predetermined threshold and to program a set of storage cells…

Non-Volatile Memory Systems with Multi-Write Direction Memory Units

Granted: May 4, 2017
Application Number: 20170125104
Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an…

Smart Skip Verify Mode For Programming A Memory Device

Granted: May 4, 2017
Application Number: 20170125117
Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum…

RERAM MIM STRUCTURE FORMATION

Granted: May 4, 2017
Application Number: 20170125483
Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx)…

Scan Chain Circuits In Non-Volatile Memory

Granted: April 27, 2017
Application Number: 20170115342
A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a…

SYSTEM FOR HANDLING ERRATIC WORD LINES FOR NON-VOLATILE MEMORY

Granted: April 27, 2017
Application Number: 20170116075
A non-volatile storage system identifies a word line with an open neighbor word line and determines whether data stored in non-volatile memory cells connected to the identified word line has an error condition. If the data does have an error condition, then an attempt is made to fix the data and the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data.

THREE DIMENSIONAL NON-VOLATILE MEMORY WITH CURRENT SENSING PROGRAMMING STATUS

Granted: April 27, 2017
Application Number: 20170117035
A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of…

SOURCE LINE DRIVER FOR THREE DIMENSIONAL NON-VOLATILE MEMORY

Granted: April 27, 2017
Application Number: 20170117036
A non-volatile storage system includes a plurality of non-volatile memory cells configured to form a monolithic three dimensional memory structure, a plurality of bit lines connected to the memory cells, a plurality of source lines connected to the memory cells, a plurality of bit line drivers connected to the bit lines and a plurality of source line drivers connected to the source lines and the bit lines. The source line drivers apply voltages to the source lines based on bit line…

THREE DIMENSIONAL NON-VOLATILE MEMORY WITH SHORTING SOURCE LINE/BIT LINE PAIRS

Granted: April 27, 2017
Application Number: 20170117037
A non-volatile storage system dedicates a subset of blocks to be used for shorting source lines to bit lines at periodic positions along the bit lines during certain memory operations.

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY DEVICES WITH SIDE SOURCE LINE AND MECHANICAL SUPPORT

Granted: April 27, 2017
Application Number: 20170117289
A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

Systems and Methods for Sampling Data at a Non-Volatile Memory System

Granted: April 20, 2017
Application Number: 20170109040
Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb…