Sandisk Patent Applications

SUB-BLOCK MODE FOR NON-VOLATILE MEMORY

Granted: June 22, 2017
Application Number: 20170178736
Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one…

BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE

Granted: June 22, 2017
Application Number: 20170179101
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an…

VOLTAGE GENERATOR TO COMPENSATE FOR PROCESS CORNER AND TEMPERATURE VARIATIONS

Granted: June 15, 2017
Application Number: 20170169867
The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length…

ON-DIE MEASUREMENT TECHNIQUE FOR I/O DC PARAMETERS VOL AND VOH

Granted: June 8, 2017
Application Number: 20170160317
A high output voltage VOH level and a low output voltage VOL level parametric test system may include test circuitry coupled to output nodes of input/output (I/O) driver circuits. The test circuitry may source and sink current to the output nodes while the I/O driver circuits are in pull down and pull up states, respectively, in order to generate output voltages on the output nodes. The parametric test system may compare the output voltages with a plurality of high and low reference…

VERTICAL RESISTOR IN 3D MEMORY DEVICE WITH TWO-TIER STACK

Granted: June 8, 2017
Application Number: 20170162592
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends…

FLOATING STAIRCASE WORD LINES AND PROCESS IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES

Granted: June 1, 2017
Application Number: 20170154845
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of…

METHOD OF FABRICATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES

Granted: June 1, 2017
Application Number: 20170154925
A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the…

Memory System and Method for Improving Write Performance in a Multi-Die Environment

Granted: May 18, 2017
Application Number: 20170139590
A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are…

State Dependent Sensing For Wordline Interference Correction

Granted: May 18, 2017
Application Number: 20170140814
A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower…

MEMORY CELLS INCLUDING VERTICALLY ORIENTED ADJUSTABLE RESISTANCE STRUCTURES

Granted: May 18, 2017
Application Number: 20170141304
A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

MULTI-PROCESSOR NON-VOLATILE MEMORY SYSTEM HAVING A LOCKLESS FLOW DATA PATH

Granted: May 4, 2017
Application Number: 20170123696
A system and method is disclosed for managing a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors and a shared data queue in a cyclic data buffer. Each of the plurality of processors may manage a separate pointer pointing to a different entry of the shared data queue and multiple ones of the processors may concurrently access or update entries in the shared data queue.

SYSTEM AND METHOD FOR UTILIZATION OF A DATA BUFFER BY COMMAND COMPLETION IN PARTS

Granted: May 4, 2017
Application Number: 20170123721
Systems and methods for managing transfer of data into and out of a host data buffer of a host are disclosed. In one implementation, a partial write completion module of a storage system retrieves from the host, stores in a memory, and acknowledges retrieving and storing with a partial write completion message, each subset of a larger set of data associated with a host write command. The host may utilize received partial write completion messages to release and use the portion of the…

SYSTEM AND METHOD FOR UTILIZATION OF A DATA BUFFER

Granted: May 4, 2017
Application Number: 20170123722
Systems and methods for managing transfer of data into and out of a host data buffer of a host are disclosed. In one implementation, a partial write completion module of a storage system retrieves from the host, stores in a memory, and acknowledges retrieving and storing with a partial write completion message, each subset of a larger set of data associated with a host write command. The host may utilize received partial write completion messages to release and use the portion of the…

SYSTEM AND METHOD FOR UTILIZATION OF A DATA BUFFER IN A STORAGE DEVICE

Granted: May 4, 2017
Application Number: 20170123991
Systems and methods for managing a data buffer of a non-volatile memory system are disclosed. The method may include a controller of a storage system retrieving host data, storing the retrieved data in a data buffer and transferring the data to a non-volatile memory. The controller may then overwrite the retrieved data in the data buffer as soon as the retrieved data has been transferred to the non-volatile memory die but prior to sending a command to program that data to the…

Handling Of Plane Failure In Non-Volatile Storage

Granted: May 4, 2017
Application Number: 20170123994
Technology is described herein for reclaiming a memory device that has a defective plane. A solution allows a memory device with a defective plane to operate as a single plane device. The memory device with the defective plane may be used without any changes to the memory controller. Thus, the memory controller can send single plane commands to the memory device with the defective plane by using single plane addressing. The memory device may have logic that properly translates the single…

DYNAMIC THRESHOLD VOLTAGE COMPACTION FOR NON-VOLATILE MEMORY

Granted: May 4, 2017
Application Number: 20170125087
Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.

PROGRAM SEQUENCING

Granted: May 4, 2017
Application Number: 20170125101
Apparatuses, systems, methods, and computer program products are disclosed for program sequencing. An apparatus includes a block of non-volatile storage cells having a plurality of word lines. The word lines are organized into a monotonically increasing sequence. The apparatus includes a controller for the block. The controller is configured to program a set of storage cells of a word line to one or more storage states above a predetermined threshold and to program a set of storage cells…

Non-Volatile Memory Systems with Multi-Write Direction Memory Units

Granted: May 4, 2017
Application Number: 20170125104
Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an…

Smart Skip Verify Mode For Programming A Memory Device

Granted: May 4, 2017
Application Number: 20170125117
Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum…

RERAM MIM STRUCTURE FORMATION

Granted: May 4, 2017
Application Number: 20170125483
Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx)…