SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
Granted: April 18, 2024
Application Number:
20240128132
A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.
ROTATABLE TEM GRID HOLDER FOR IMPROVED FIB THINNING PROCESS
Granted: April 18, 2024
Application Number:
20240128046
A rotatable transmission electron microscope (TEM) grid holder includes first and second legs orthogonally positioned with respect to each other. Each clamp holder leg is configured to be received within a hole in a main stage supporting the rotatable TEM grid holder. When the first leg of the clamp holder is affixed within the main stage, the sample has a first orientation with respect to the FIB, and when second leg of the clamp holder is affixed within the main stage, the sample has a…
NON-VOLATILE MEMORY WITH OVERDRIVE VOLTAGE ZONING TO COMPENSATE FOR REDUCED MARGINS
Granted: April 18, 2024
Application Number:
20240127895
During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.
PROGRAM PULSE DURATION INCREASE FOR NAND PROGRAM FAILURE
Granted: April 18, 2024
Application Number:
20240127891
Technology is disclosed herein in which a duration of a program pulse used to program non-volatile memory cells such as NAND may be increased responsive to a programming failure using a shorter duration program pulse. The duration of at least one program pulse may be increased for at least one group of memory cells in response to a failure to program a group using a default program pulse duration. The group that experiences the increased duration program pulse may be the same group for…
SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
Granted: April 18, 2024
Application Number:
20240125846
A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.
HIGH PERFORMANCE VERIFY TECHNIQUES IN A MEMORY DEVICE
Granted: April 4, 2024
Application Number:
20240112744
The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is…
GATE-INDUCED DRAIN LEAKAGE PRE-CHARGE IN SUB-BLOCK MODE FOR THREE OR MORE TIER NON-VOLATILE MEMORY STRUCTURE
Granted: April 4, 2024
Application Number:
20240112743
An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage…
NON-VOLATILE MEMORY WITH DIFFERENT WORD LINE TO WORD LINE PITCHES
Granted: April 4, 2024
Application Number:
20240112735
In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.
NON-VOLATILE MEMORY WITH REDUCED WORD LINE SWITCH AREA
Granted: April 4, 2024
Application Number:
20240111440
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile…
PREVENTING ERASE DISTURB IN NAND
Granted: March 28, 2024
Application Number:
20240105271
Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the…
BIT LINE MODULATION TO COMPENSATE FOR CELL SOURCE VARIATION
Granted: March 28, 2024
Application Number:
20240105269
Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level…
ERASE METHOD FOR NON-VOLATILE MEMORY WITH MULTIPLE TIERS
Granted: March 28, 2024
Application Number:
20240105265
A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.
NON-VOLATILE MEMORY WITH SUB-PLANES HAVING INDIVIDUALLY BIASABLE SOURCE LINES
Granted: March 28, 2024
Application Number:
20240105262
To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.
NON-VOLATILE MEMORY WITH PROGRAMMABLE RESISTANCE NON-DATA WORD LINE
Granted: March 28, 2024
Application Number:
20240103742
In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be…
HIGH DENSITY SEMICONDUCTOR DEVICE INCLUDING INTEGRATED CONTROLLER, LOGIC CIRCUIT AND MEMORY DIES
Granted: March 21, 2024
Application Number:
20240096850
An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the…
APPARATUS AND METHODS FOR BONDING PAD REDISTRIBUTION LAYERS IN INTEGRATED CIRCUITS
Granted: March 21, 2024
Application Number:
20240096826
An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The…
PERSISTENT MEMORY MANAGEMENT
Granted: March 21, 2024
Application Number:
20240095233
Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality…
SUB-BLOCK STATUS DEPENDENT DEVICE OPERATION
Granted: March 14, 2024
Application Number:
20240087650
A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the…
NAND STRING READ VOLTAGE ADJUSTMENT
Granted: March 14, 2024
Application Number:
20240086074
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a…
BUNDLE MULTIPLE TIMING PARAMETERS FOR FAST SLC PROGRAMMING
Granted: March 7, 2024
Application Number:
20240078028
Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the…
