Sandisk Patent Applications

Systems and Methods for Performing Data Recovery in a Memory System

Granted: January 5, 2017
Application Number: 20170004052
Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a…

MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER

Granted: December 29, 2016
Application Number: 20160378379
A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a…

CLOCK FREEZING TECHNIQUE FOR CHARGE PUMPS

Granted: December 29, 2016
Application Number: 20160380532
Methods and systems for generating voltages greater than a supply voltage are described. A charge pump system may generate a boosted output voltage greater than the supply voltage using one or more charge pump stages that are arranged in series between the supply voltage and the boosted output voltage. The charge pump system may include clock freezing circuitry that eliminates glitches in clock signals used for driving the one or more charge pump stages. In one example, the clock…

Reticle With Reduced Transmission Regions For Detecting A Defocus Condition In A Lithography Process

Granted: December 22, 2016
Application Number: 20160370598
A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. The regions may be adjacent to openings in an opaque material at the bottom of the reticle to shield the openings from a portion of the light which illuminates the reticle from the top. As a result, the light which exits the reticle and is…

Memory System and Method for Power Management

Granted: December 22, 2016
Application Number: 20160370841
A memory system and method for power management are disclosed. In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in…

Memory System and method for power management

Granted: December 22, 2016
Application Number: 20160372160
A memory system and method for power management are disclosed. In one embodiment, a memory system maintains a variable credit value indicating an amount of power currently available for memory operations in the memory system, the variable credit value having an upper limit that reflects a maximum power limit for the memory system. The memory system receives a command to perform a memory operation, wherein a plurality of resources are required to perform the memory operation, each…

FAST SCAN TO DETECT BIT LINE DISCHARGE TIME

Granted: December 22, 2016
Application Number: 20160372200
Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first…

SENSE AMPLIFIER DESIGN FOR RAMP SENSING

Granted: December 22, 2016
Application Number: 20160372205
Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is…

Data Retention in a Memory Block Based on Local Heating

Granted: December 15, 2016
Application Number: 20160364175
A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.

Reducing Hot Electron Injection Type Of Read Disturb In 3D Non-Volatile Memory For Edge Word Lines

Granted: December 8, 2016
Application Number: 20160358662
Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word…

MULTI-VT SENSING METHOD BY VARYING BIT LINE VOLTAGE

Granted: December 8, 2016
Application Number: 20160358664
Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell threshold voltage levels may be concurrently verified by applying a word line voltage to a plurality of memory cells, applying two or more different bit line voltages to the plurality of memory cells, and sensing the plurality of memory cells while the two or more different bit line voltages are applied to the plurality of memory…

Smart Ring with Biometric Sensor

Granted: December 1, 2016
Application Number: 20160350581
A ring with a biometric sensor is provided. In one embodiment, the ring comprises a ring body, a biometric sensor positioned in the ring body and configured to sense a biometric feature, a memory configured to store a biometric feature of an authorized user, and a controller. The controller is configured to determine whether the biometric feature sensed by the biometric sensor matches the biometric feature stored in the memory, and in response to determining that the biometric feature…

MULTI-STATE PROGRAMMING FOR NON-VOLATILE MEMORY

Granted: December 1, 2016
Application Number: 20160351254
A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data…

SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY

Granted: December 1, 2016
Application Number: 20160351435
A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap.

Multiple Junction Thin Film Transistor

Granted: December 1, 2016
Application Number: 20160351722
A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p?…

BLOCK BEHAVIOR TRACKING IN A MEMORY SYSTEM

Granted: November 24, 2016
Application Number: 20160342494
A storage device with a memory may include memory block health monitoring and behavior tracking Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read…

SYSTEM AND METHOD FOR MEMORY INTEGRATED CIRCUIT CHIP WRITE ABORT INDICATION

Granted: November 24, 2016
Application Number: 20160343448
Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being…

READ DISTURB DETECTION IN OPEN BLOCKS

Granted: November 24, 2016
Application Number: 20160343449
A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in…

STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE MEMORY

Granted: November 24, 2016
Application Number: 20160343454
A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the…

SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY

Granted: November 24, 2016
Application Number: 20160343608
A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and…