Sandisk Patent Applications

SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY

Granted: February 23, 2017
Application Number: 20170053929
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

RING OSCILLATORS FOR TEMPERATURE DETECTION IN WIDEBAND SUPPLY NOISE ENVIRONMENTS

Granted: February 9, 2017
Application Number: 20170038264
A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged,…

BLOCK MANAGEMENT IN A DUAL WRITE MEMORY SYSTEM

Granted: February 2, 2017
Application Number: 20170031612
A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for…

SELF-DESCRIBING CLUSTER ASSOCIATION

Granted: February 2, 2017
Application Number: 20170031624
A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify…

Memory System and Method of Generating a Seed Value

Granted: February 2, 2017
Application Number: 20170031656
A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

THREE DIMENSIONAL NAND MEMORY HAVING IMPROVED CONNECTION BETWEEN SOURCE LINE AND IN-HOLE CHANNEL MATERIAL AS WELL AS REDUCED DAMAGE TO IN-HOLE LAYERS

Granted: February 2, 2017
Application Number: 20170033121
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory…

DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS

Granted: January 26, 2017
Application Number: 20170025182
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines…

Memory System and Method for Adaptive Auto-Sleep and Background Operations

Granted: January 26, 2017
Application Number: 20170024002
A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are…

OPTIMISTIC READ OPERATION

Granted: January 26, 2017
Application Number: 20170024127
A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data…

Systems and Methods for Performing Data Recovery in a Memory System

Granted: January 5, 2017
Application Number: 20170004052
Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a…

MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER

Granted: December 29, 2016
Application Number: 20160378379
A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a…

CLOCK FREEZING TECHNIQUE FOR CHARGE PUMPS

Granted: December 29, 2016
Application Number: 20160380532
Methods and systems for generating voltages greater than a supply voltage are described. A charge pump system may generate a boosted output voltage greater than the supply voltage using one or more charge pump stages that are arranged in series between the supply voltage and the boosted output voltage. The charge pump system may include clock freezing circuitry that eliminates glitches in clock signals used for driving the one or more charge pump stages. In one example, the clock…

Reticle With Reduced Transmission Regions For Detecting A Defocus Condition In A Lithography Process

Granted: December 22, 2016
Application Number: 20160370598
A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. The regions may be adjacent to openings in an opaque material at the bottom of the reticle to shield the openings from a portion of the light which illuminates the reticle from the top. As a result, the light which exits the reticle and is…

Memory System and Method for Power Management

Granted: December 22, 2016
Application Number: 20160370841
A memory system and method for power management are disclosed. In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in…

Memory System and method for power management

Granted: December 22, 2016
Application Number: 20160372160
A memory system and method for power management are disclosed. In one embodiment, a memory system maintains a variable credit value indicating an amount of power currently available for memory operations in the memory system, the variable credit value having an upper limit that reflects a maximum power limit for the memory system. The memory system receives a command to perform a memory operation, wherein a plurality of resources are required to perform the memory operation, each…

FAST SCAN TO DETECT BIT LINE DISCHARGE TIME

Granted: December 22, 2016
Application Number: 20160372200
Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first…

SENSE AMPLIFIER DESIGN FOR RAMP SENSING

Granted: December 22, 2016
Application Number: 20160372205
Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is…

Data Retention in a Memory Block Based on Local Heating

Granted: December 15, 2016
Application Number: 20160364175
A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.

Reducing Hot Electron Injection Type Of Read Disturb In 3D Non-Volatile Memory For Edge Word Lines

Granted: December 8, 2016
Application Number: 20160358662
Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word…

MULTI-VT SENSING METHOD BY VARYING BIT LINE VOLTAGE

Granted: December 8, 2016
Application Number: 20160358664
Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell threshold voltage levels may be concurrently verified by applying a word line voltage to a plurality of memory cells, applying two or more different bit line voltages to the plurality of memory cells, and sensing the plurality of memory cells while the two or more different bit line voltages are applied to the plurality of memory…