Sandisk Patent Applications

EXTENDING HARDWARE QUEUES WITH SOFTWARE QUEUES

Granted: March 16, 2017
Application Number: 20170075572
A storage device with a memory may implement software queueing that can supplement hardware accelerated queueing mechanisms. A software queue supplementing a hardware queue can extend the size and allow pending operations to proceed even if the hardware queue is saturated. The use of software-based queues may extend processing capacity in a hardware-accelerated front-end storage device architecture. The software queue may process excess commands that cannot be handled by a hardware queue…

SYSTEM AND METHOD FOR COUNTER FLUSH FREQUENCY

Granted: March 16, 2017
Application Number: 20170075593
Apparatus and method for determining when to save values of read counters are disclosed. Read counters store values that indicate the number of reads in respective blocks of a memory device. The values of the read counters may be stored in volatile memory, and may be periodically stored to non-volatile memory. The frequency at which the values of the read counters are stored to non-volatile memory may be dependent on the read disturb effect. One measure of the read disturb effect may be…

MULTIPLE SCHEDULING SCHEMES FOR HANDLING READ REQUESTS

Granted: March 16, 2017
Application Number: 20170075622
A non-volatile memory system may include a controller that issues data transfer commands to have data units associated with a host read request transferred from non-volatile memory to a temporary storage area before the data is sent to a host. The controller may be configured to generate a schedule that identifies when the data transfer commands are issued. The schedule may be generated according to one of a plurality of scheduling schemes, each with a different priority in having the…

PRESERVING READ LOOK AHEAD DATA IN AUXILIARY LATCHES

Granted: March 16, 2017
Application Number: 20170075629
A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be…

Verify Operations Using Different Sense Node Voltages In A Memory Device

Granted: March 16, 2017
Application Number: 20170076812
Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify…

Storage Device and Method for Detecting and Handling Burst Operations

Granted: March 9, 2017
Application Number: 20170068451
A storage device and method for detecting and handling burst operations are provided. In one embodiment, a method for operating a storage device in burst mode is provided. The storage device senses a change in behavior of a host in communication with the storage device, determines whether the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode by comparing the sensed change in behavior with prior changes in behavior that…

System and Method for File Detection and Usage During Compaction

Granted: March 9, 2017
Application Number: 20170068470
A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in…

System and Method for Selectively Routing Cached Objects

Granted: March 9, 2017
Application Number: 20170068684
A monitoring application and method for using a monitoring application are disclosed. The monitoring application is configured to manage file system objects in a memory device layer (including copying of the file system objects) and is configured to manage one or more data structures to enable the management of the file system objects to be transparent to the application layer and/or the operating system layer.

Memory System and Method for Reducing Peak Current Consumption

Granted: March 2, 2017
Application Number: 20170060461
A memory system and method for reducing peak current consumption. In one embodiment, a method is provided that is performed in a memory system comprising a memory with a plurality of blocks, wherein each block has a peak current consumption. In this method, a plurality of metablocks is created, wherein each metablock is created by grouping together blocks with complementary peak current consumption. Next, the metablocks are programmed. Because each of the metablocks has blocks with…

Memory System and Method for Performing Garbage Collection on Blocks Based on Their Obsolescence Patterns

Granted: March 2, 2017
Application Number: 20170060738
A memory system and method are provided for performing garbage collection on blocks based on their obsolescence patterns. In one embodiment, a controller of a memory system classifies each of the plurality of blocks based on its obsolescence pattern and performs garbage collection only on blocks classified with similar obsolescence patterns. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

NAND Boosting Using Dynamic Ramping of Word Line Voltages

Granted: March 2, 2017
Application Number: 20170062068
Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be…

DYNAMIC MANAGEMENT OF PROGRAMMING STATES TO IMPROVE ENDURANCE

Granted: March 2, 2017
Application Number: 20170062069
A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC)…

SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY

Granted: February 23, 2017
Application Number: 20170053929
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

RING OSCILLATORS FOR TEMPERATURE DETECTION IN WIDEBAND SUPPLY NOISE ENVIRONMENTS

Granted: February 9, 2017
Application Number: 20170038264
A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged,…

BLOCK MANAGEMENT IN A DUAL WRITE MEMORY SYSTEM

Granted: February 2, 2017
Application Number: 20170031612
A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for…

SELF-DESCRIBING CLUSTER ASSOCIATION

Granted: February 2, 2017
Application Number: 20170031624
A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify…

Memory System and Method of Generating a Seed Value

Granted: February 2, 2017
Application Number: 20170031656
A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

THREE DIMENSIONAL NAND MEMORY HAVING IMPROVED CONNECTION BETWEEN SOURCE LINE AND IN-HOLE CHANNEL MATERIAL AS WELL AS REDUCED DAMAGE TO IN-HOLE LAYERS

Granted: February 2, 2017
Application Number: 20170033121
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory…

Memory System and Method for Adaptive Auto-Sleep and Background Operations

Granted: January 26, 2017
Application Number: 20170024002
A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are…

OPTIMISTIC READ OPERATION

Granted: January 26, 2017
Application Number: 20170024127
A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data…