Sandisk Patent Applications

NON-VOLATILE MEMORY HAVING INDIVIDUALLY OPTIMIZED SILICIDE CONTACTS AND PROCESS THEREFOR

Granted: July 20, 2017
Application Number: 20170207092
In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication…

FAST SETTLING LOW DROPOUT VOLTAGE REGULATOR

Granted: July 13, 2017
Application Number: 20170199536
Methods and systems for reducing the settling time of a voltage regulator are described. In some cases, the settling time of the voltage regulator may be reduced by detecting that the voltage regulator is transitioning from a standby mode to an active mode and drawing additional current from the output of the voltage regulator during a current boosting phase. The current boosting phase may correspond with a current boosting pulse that is initiated when an enable signal is received from a…

DATA PATH CONTROL FOR NON-VOLATILE MEMORY

Granted: July 13, 2017
Application Number: 20170199668
Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations.…

PHYSICAL ADDRESSING SCHEMES FOR NON-VOLATILE MEMORY SYSTEMS EMPLOYING MULTI-DIE INTERLEAVE SCHEMES

Granted: July 13, 2017
Application Number: 20170199703
A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows…

NON-VOLATILE MEMORY WITH EFFICIENT PROGRAMMING

Granted: July 13, 2017
Application Number: 20170200501
A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select…

Memory System and Method for Power Management for Reducing a Variable Credit Value By a Computed Consumed Energy Value for Each Corresponding Updated Cycle

Granted: July 6, 2017
Application Number: 20170192722
In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time…

Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization

Granted: June 29, 2017
Application Number: 20170185299
A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by…

PARITY STORAGE MANAGEMENT

Granted: June 29, 2017
Application Number: 20170185472
Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.

KEY-VALUE STORE WITH PARTIAL DATA ACCESS

Granted: June 29, 2017
Application Number: 20170185625
Apparatuses, systems, methods, and computer program products are disclosed for key-value stores with partial data access. An interface module is configured to receive a data object for storage in a key-value store. The data object may include a key and a value. A block object module is configured to generate a plurality of block objects smaller than the data object. A block object may include a new key and a new value. The new key may be based on the key for the data object and on…

SOLID STATE DRIVE OPTIMIZED FOR WAFERS

Granted: June 29, 2017
Application Number: 20170186731
An SSD with a package optimized for semiconductor wafers is configured by thinning a plurality of undiced wafers and stacking the wafers. The wafers are connected to each other by TSV. A subset of the wafers include memory circuits. One of the wafer not in the subset includes peripheral circuits. A casing houses the wafers.

SUB-BLOCK MODE FOR NON-VOLATILE MEMORY

Granted: June 22, 2017
Application Number: 20170178736
Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one…

BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE

Granted: June 22, 2017
Application Number: 20170179101
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an…

VOLTAGE GENERATOR TO COMPENSATE FOR PROCESS CORNER AND TEMPERATURE VARIATIONS

Granted: June 15, 2017
Application Number: 20170169867
The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length…

ON-DIE MEASUREMENT TECHNIQUE FOR I/O DC PARAMETERS VOL AND VOH

Granted: June 8, 2017
Application Number: 20170160317
A high output voltage VOH level and a low output voltage VOL level parametric test system may include test circuitry coupled to output nodes of input/output (I/O) driver circuits. The test circuitry may source and sink current to the output nodes while the I/O driver circuits are in pull down and pull up states, respectively, in order to generate output voltages on the output nodes. The parametric test system may compare the output voltages with a plurality of high and low reference…

VERTICAL RESISTOR IN 3D MEMORY DEVICE WITH TWO-TIER STACK

Granted: June 8, 2017
Application Number: 20170162592
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends…

FLOATING STAIRCASE WORD LINES AND PROCESS IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES

Granted: June 1, 2017
Application Number: 20170154845
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of…

METHOD OF FABRICATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES

Granted: June 1, 2017
Application Number: 20170154925
A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the…

Memory System and Method for Improving Write Performance in a Multi-Die Environment

Granted: May 18, 2017
Application Number: 20170139590
A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are…

State Dependent Sensing For Wordline Interference Correction

Granted: May 18, 2017
Application Number: 20170140814
A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower…

MEMORY CELLS INCLUDING VERTICALLY ORIENTED ADJUSTABLE RESISTANCE STRUCTURES

Granted: May 18, 2017
Application Number: 20170141304
A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.