Sandisk Patent Grants

Storage device blister tray

Granted: September 5, 2017
Patent Number: D796315

Storage device blister tray

Granted: September 5, 2017
Patent Number: D796316

Voltage regulator with fast overshoot settling response

Granted: September 5, 2017
Patent Number: 9753476
A voltage regulator circuit is provided in which voltage overshoots are quickly dissipated using a discharge path which is connected to an output of the voltage regulator. Circuitry for controlling the discharge path is provided using internal currents of an error amplifier to provide a space-efficient and power-efficient design with a fast response. Moreover, hysteresis can be provided to avoid toggling between discharge and no discharge, and to avoid undershoot when discharging the…

Dynamic clock rate control for power reduction

Granted: September 5, 2017
Patent Number: 9753522
A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuitry may set or adjust the rates of variable-rate clock signals linearly in…

Tracking intermix of writes and un-map commands across power cycles

Granted: September 5, 2017
Patent Number: 9753649
Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical…

High-priority NAND operations management

Granted: September 5, 2017
Patent Number: 9753653
Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the…

Dynamic reconditioning of charge trapped based memory

Granted: September 5, 2017
Patent Number: 9753657
A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data…

Bit line charging for a device

Granted: September 5, 2017
Patent Number: 9754645
An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple…

Vacancy-modulated conductive oxide resistive RAM device including an interfacial oxygen source layer

Granted: September 5, 2017
Patent Number: 9754665
A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium…

Three-dimensional NAND non-volatile memory and DRAM memory devices on a single substrate

Granted: September 5, 2017
Patent Number: 9754667
A three-dimensional NAND stacked non-volatile memory array and a DRAM memory array are provided. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are integrated on a single substrate.

Three-dimensional memory device containing an aluminum oxide etch stop layer for backside contact structure and method of making thereof

Granted: September 5, 2017
Patent Number: 9754820
Collateral etching of a dielectric material around a trench during formation of a substrate contact via structure can be avoided employing an aluminum oxide layer. The aluminum oxide layer functions as an etch stop layer during an anisotropic etch that removes horizontal portions of an insulating material layer to form an insulating spacer. The aluminum oxide layer may be a conformal or a non-conformal material layer, and may, or may not, include a horizontal portion that overlies an…

Uniform thickness blocking dielectric portions in a three-dimensional memory structure

Granted: September 5, 2017
Patent Number: 9754956
A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from…

Three-dimensional memory devices having a shaped epitaxial channel portion and method of making thereof

Granted: September 5, 2017
Patent Number: 9754958
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the…

Multi-tier memory stack structure containing two types of support pillar structures

Granted: September 5, 2017
Patent Number: 9754963
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support pillar structures are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. Memory stack structures and second support pillar structures are formed through the second…

Vertical thin film transistors with surround gates

Granted: September 5, 2017
Patent Number: 9754999
A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.

Method and system for improving error correction in data storage

Granted: August 29, 2017
Patent Number: 9747157
A method of operation of a data storage system includes: monitoring a data interface bus, the monitoring by a non-volatile memory controller; activating a zero bit counter for detecting a ratio of 1's to 0's on the data interface bus; and adjusting a threshold voltage (Vth), based on the ratio of the 1's to the 0's from the zero bit counter, by the non-volatile memory controller.

Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Granted: August 29, 2017
Patent Number: 9748266
A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate…

Three dimensional NAND device with channel contacting conductive source line and method of making thereof

Granted: August 29, 2017
Patent Number: 9748267
A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source…

Memory cells including vertically oriented adjustable resistance structures

Granted: August 29, 2017
Patent Number: 9748479
A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

Interleaved layered decoder for low-density parity check codes

Granted: August 29, 2017
Patent Number: 9748973
A controller is configured to access information to generate data blocks. The controller includes a data block interleaver and a low-density parity check (LDPC) decoder. The data block interleaver is configured to interleave the data blocks to generate interleaved data blocks. The LDPC decoder is configured to decode the interleaved data blocks.