Sandisk Patent Grants

Timing optimized implementation of algorithm to reduce switching rate on high throughput wide buses

Granted: July 18, 2017
Patent Number: 9710012
A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup…

Method and computing device for controlling bandwidth of swap operations

Granted: July 18, 2017
Patent Number: 9710198
The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area.

On chip dynamic read level scan and error detection for nonvolatile storage

Granted: July 18, 2017
Patent Number: 9710325
Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from…

Error correction based on historical bit error data

Granted: July 18, 2017
Patent Number: 9710329
A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability…

Dynamic threshold voltage compaction for non-volatile memory

Granted: July 18, 2017
Patent Number: 9711211
Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.

Content addressable memory cells and memory arrays

Granted: July 18, 2017
Patent Number: 9711222
A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2.

Regrouping and skipping cycles in non-volatile memory

Granted: July 18, 2017
Patent Number: 9711225
A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped…

Non-volatile memory with in field failure prediction using leakage detection

Granted: July 18, 2017
Patent Number: 9711227
To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.

3D NAND with partial block erase

Granted: July 18, 2017
Patent Number: 9711229
Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more…

System solution for first read issue using time dependent read voltages

Granted: July 18, 2017
Patent Number: 9711231
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing…

Shallow trench isolation trenches and methods for NAND memory

Granted: July 18, 2017
Patent Number: 9711390
A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and…

Memory hole structure in three dimensional memory

Granted: July 18, 2017
Patent Number: 9711522
In a three dimensional nonvolatile memory, memory holes extend vertically through two or more physical levels in which memory cells are formed. Memory hole structures are formed in memory holes to include vertical channels. Vertical trenches are subsequently formed to divide memory hole structures into two or more vertical NAND strings.

Three-dimensional memory device containing plural select gate transistors having different characteristics and method of making thereof

Granted: July 18, 2017
Patent Number: 9711524
A stack of material layers includes first material layers, second material layers located between a respective pair of an overlying first material layer and an underlying first material layer, and at least one temporary material layer located between a respective pair of an overlying first material layer and an underlying first material layer. After formation of a memory opening and a memory stack structure, at least one first backside recess is formed by removing the at least one…

Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures

Granted: July 18, 2017
Patent Number: 9711530
Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device. The compositionally modulated charge storage layer can be formed by providing an oxygen-containing dielectric silicon compound layer outside a tunneling dielectric layer, and subsequently nitriding portions of the oxygen-containing dielectric silicon compound layer only at levels of the…

Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers

Granted: July 18, 2017
Patent Number: 9711532
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory…

Vertical thin film transistor selection devices and methods of fabrication

Granted: July 18, 2017
Patent Number: 9711650
Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath…

Sense amplifier with integrating capacitor and methods of operation

Granted: July 11, 2017
Patent Number: 9704572
A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a…

Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory

Granted: July 11, 2017
Patent Number: 9704588
Reduced errors when sensing non-volatile memory are provided by applying a current spike or preconditioning current for a group of memory cells included a selected cell. During a sense operation, a preconditioning current can be passed through a group of non-volatile memory cells. The preconditioning current is provided prior to applying at least one reference voltage to a selected word line. The preconditioning current may simulate a cell current passing through the channel during a…

Temperature independent reference current generation for calibration

Granted: July 11, 2017
Patent Number: 9704591
Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient…

Self-detecting a heating event to non-volatile storage

Granted: July 11, 2017
Patent Number: 9704595
Techniques are provided for non-volatile storage self-detecting that a heating event has occurred to the non-volatile storage. One example of the heating event is an Infrared (IR) reflow process. In one aspect, a block of memory cells in a memory device are put through a number of program/erase cycles. A group of the memory cells in the cycled block are programmed to a reference threshold voltage distribution. Some time may pass after programming the cycled block. The memory device…