Sandisk Patent Grants

Data encoding techniques for a device

Granted: August 15, 2017
Patent Number: 9734009
A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity…

Method and system for managing background operations in a multi-layer memory

Granted: August 15, 2017
Patent Number: 9734050
A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die…

Apparatus, system, and method for a device shared between multiple independent hosts

Granted: August 15, 2017
Patent Number: 9734086
The invention includes a proxy request receiver module and a proxy request command module. The proxy request receiver module executes on a designated command proxy host and receives a proxy request from a requesting host. The requesting host is one of two or more hosts. Each of the hosts executes an operating system independent from the other hosts and a shared device. One of the hosts is designated as the command proxy host. A system bus connects the hosts and shared device. The proxy…

Memory bus management

Granted: August 15, 2017
Patent Number: 9734098
A method of managing a memory bus includes identifying sub-operations required for execution of commands, maintaining a list of released sub-operations containing only released unexecuted sub-operations directed to individual dies that are identified as available, accessing the dies until the list is empty, subsequently, polling to identify dies that are available, and subsequently resuming accessing the dies by executing only sub-operations from the list until the list is empty.

Low complexity partial parallel architectures for Fourier transform and inverse Fourier transform over subfields of a finite field

Granted: August 15, 2017
Patent Number: 9734129
Low complexity partial parallel architectures for performing a Fourier transform and an inverse Fourier transform over subfields of a finite field are described. For example, circuits to perform the Fourier transforms and the inverse Fourier transform as described herein may have architectures that have simplified multipliers and/or computational units as compared to traditional Fourier transform circuits and traditional inverse Fourier transform circuits that have partial parallel…

Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

Granted: August 15, 2017
Patent Number: 9734899
A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory…

Disturb condition detection for a resistive random access memory

Granted: August 15, 2017
Patent Number: 9734903
A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed…

Method and system for asynchronous die operations in a non-volatile memory

Granted: August 15, 2017
Patent Number: 9734911
A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may…

Implementation of VMCO area switching cell to VBL architecture

Granted: August 15, 2017
Patent Number: 9735202
Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of…

Measuring memory wear and data retention individually based on cell voltage distributions

Granted: August 8, 2017
Patent Number: 9727276
A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear,…

Storage device and method for enabling hidden functionality

Granted: August 8, 2017
Patent Number: 9727277
A storage device and method for enabling hidden functionality are provided. In one embodiment, a storage device is provided comprising an interface a memory, and a controller. The controller is configured to receive a series of read and/or write commands to the memory from the host device. If the series of read and/or write commands received from the host device matches an expected pattern of read and/or write commands, irrespective what data is being read or written by those commands,…

Multi-level table deltas

Granted: August 8, 2017
Patent Number: 9727453
A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each…

Storage system supporting replacement of content in a storage device

Granted: August 8, 2017
Patent Number: 9727571
A file replacement system includes a storage device, a host, and a server. In a file replacement transaction one or more files that are stored in the storage device are replaced in the storage device by one or more files that are provided by the server. The storage device monitors access to the files stored therein and updates an access tracking table with segment access information that pertains to access to segments of the files. While the file replacement transaction is in progress,…

Non-volatile memory systems with multi-write direction memory units

Granted: August 8, 2017
Patent Number: 9728262
Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an…

Method and device for iteratively updating read voltages

Granted: August 8, 2017
Patent Number: 9728263
A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage…

Set of stepped surfaces formation for a multilevel interconnect structure

Granted: August 8, 2017
Patent Number: 9728499
A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers.…

Packaging of high performance system topology for NAND memory systems

Granted: August 8, 2017
Patent Number: 9728526
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in…

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

Granted: August 8, 2017
Patent Number: 9728546
A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions…

Three-dimensional memory device with aluminum-containing etch stop layer for backside contact structure and method of making thereof

Granted: August 8, 2017
Patent Number: 9728547
Unwanted erosion of dielectric materials around a backside contact trench can be avoided or minimized employing an aluminum oxide liner. An aluminum oxide liner can be formed inside an insulating material layer in a backside contact trench to prevent collateral etching of the insulating material at an upper portion of the backside contact trench during an anisotropic etch that forms an insulating spacer. Alternatively, an aluminum oxide layer can be employed as a backside blocking…

Multi-tier replacement memory stack structure integration scheme

Granted: August 8, 2017
Patent Number: 9728551
A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are…