Sandisk Patent Grants

Read operation for non-volatile storage with compensation for coupling

Granted: January 17, 2017
Patent Number: RE46279
Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide…

Block behavior tracking in a memory system

Granted: January 17, 2017
Patent Number: 9547571
A storage device with a memory may include memory block health monitoring and behavior tracking. Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read…

Enhanced post-write read for 3-D memory

Granted: January 17, 2017
Patent Number: 9548105
Apparatus and method for performing a post-write read in a memory device are disclosed. A memory device may include 3-dimensional memory, with the wordlines in a memory block each having multiple strings. Periodically, the memory device may analyze the wordlines for defects by performing a post-write read on a respective wordline and analyzing the read data to determine whether the respective wordline is defective. Rather than reading all of the strings for the respective wordline, less…

Word line dependent programming in a memory device

Granted: January 17, 2017
Patent Number: 9548124
A memory device includes memory cells arranged in word lines. Due to variations in the fabrication process, with width and spacing between word lines can vary, resulting in widened threshold voltage distributions. In one approach, a programming parameter is optimized for each word line based on a measurement of the threshold voltage distributions in an initial programming operation. An adjustment to the programming parameter of a word line can be based, e.g., on measurements from…

Word line look ahead read for word line to word line short detection

Granted: January 17, 2017
Patent Number: 9548129
Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation…

Non-volatile memory with prior state sensing

Granted: January 17, 2017
Patent Number: 9548130
A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control…

Non-volatile storage element with suspended charge storage region

Granted: January 17, 2017
Patent Number: 9548311
Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface…

Method of making a monolithic three dimensional NAND string using a select gate etch stop layer

Granted: January 17, 2017
Patent Number: 9548313
A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such…

System and method for redirecting airflow across an electronic assembly

Granted: January 17, 2017
Patent Number: 9549457
The system for redirecting airflow includes multiple electronic assemblies arranged adjacent to one another. Each electronic assembly includes a substrate having a substantially flat first surface and an opposing substantially flat second surface. Electronic devices are coupled to each of the first and second surfaces. Each surface also has one or more tabs coupled thereto, where each tab is configured to redirect the airflow over a least one electronic device.

Failure logging mechanism to reduce garbage collection time in partially reused bad blocks

Granted: January 10, 2017
Patent Number: 9542286
A memory system logs failures to optimize garbage collection in partial bad blocks that are reused in non-volatile memory. A failure in a primary block may be logged in an inverse global address table. A garbage collection operation can reference the log in order to automatically avoid the failure in the primary block when the primary block is picked as the source block for garbage collection. Likewise, the garbage collection operation may scan only the logged wordlines in the secondary…

Relocating data based on matching address sequences

Granted: January 10, 2017
Patent Number: 9542309
A data storage device includes a non-volatile memory and a controller. The controller is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device. Subsequent to storing the first sequence of addresses, the controller is configured to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches…

Datapath management in a memory controller

Granted: January 10, 2017
Patent Number: 9542344
A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

Multiple layer forming scheme for vertical cross point reram

Granted: January 10, 2017
Patent Number: 9543009
Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a…

Partial block erase for block programming in non-volatile memory

Granted: January 10, 2017
Patent Number: 9543023
A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of…

Storage control system with power-off time estimation mechanism and method of operation thereof

Granted: January 10, 2017
Patent Number: 9543025
A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an…

Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect

Granted: January 10, 2017
Patent Number: 9543028
Methods for reducing cross-temperature dependent word line failures using a temperature dependent sensing scheme during a sensing operation are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time, source line voltage, or bit line voltage) may be set based on a temperature of the memory cells during sensing and a word line location of the memory cells to be sensed. In one example, the memory…

Sense amplifier design for ramp sensing

Granted: January 10, 2017
Patent Number: 9543030
Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is…

In-situ support structure for line collapse robustness in memory arrays

Granted: January 10, 2017
Patent Number: 9543139
Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during…

Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors

Granted: January 10, 2017
Patent Number: 9543318
An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of…

Three-dimensional memory structure having self-aligned drain regions and methods of making thereof

Granted: January 10, 2017
Patent Number: 9543320
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around…