Sandisk Patent Grants

Program cycle skip

Granted: March 21, 2017
Patent Number: RE46348
A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some…

Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment

Granted: March 21, 2017
Patent Number: 9600184
An apparatus, system, and method are disclosed for coordinating storage requests in a multi-processor/multi-thread environment. An append/invalidate module generates a first append data storage command from a first storage request and a second append data storage command from a second storage request. The storage requests overwrite existing data with first and second data including where the first and second data have at least a portion of overlapping data. The second storage request is…

Multiheight contact via structures for a multilevel interconnect structure

Granted: March 21, 2017
Patent Number: 9601502
A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number…

Blocking oxide in memory opening integration scheme for three-dimensional memory structure

Granted: March 21, 2017
Patent Number: 9601508
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be…

High-speed multi-block-row layered decoder for low density parity check (LDPC) codes

Granted: March 21, 2017
Patent Number: 9602141
High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a…

System and method for distributed computing in non-volatile memory

Granted: March 14, 2017
Patent Number: 9594524
A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash…

Flash cache flushing method and system

Granted: March 14, 2017
Patent Number: 9594679
A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back…

Multi-state programming for non-volatile memory

Granted: March 14, 2017
Patent Number: 9595317
A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data…

Reduced level cell mode for non-volatile memory

Granted: March 14, 2017
Patent Number: 9595318
Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method…

Multi-level reversible resistance-switching memory

Granted: March 14, 2017
Patent Number: 9595321
A method is provided for operating a reversible resistance-switching memory cell. The method includes programming the reversible resistance-switching memory cell to three or more memory states while limiting the current through the memory cell to less than between about 0.1 microamp and about 30 microamps.

Word line compensation for memory arrays

Granted: March 14, 2017
Patent Number: 9595323
A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes receiving a current conducted by the word line comb, estimating a resistance of a conductive path between the word line comb and a selected word line voltage node, and generating a voltage at…

Apparatus and methods for sensing hard bit and soft bits

Granted: March 14, 2017
Patent Number: 9595325
A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Utilizing NAND strings in dummy blocks for faster bit line precharge

Granted: March 14, 2017
Patent Number: 9595338
In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times,…

Method and apparatus for refresh programming of memory cells based on amount of threshold voltage downshift

Granted: March 14, 2017
Patent Number: 9595342
Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code…

Adaptive selective bit line pre-charge for current savings and fast programming

Granted: March 14, 2017
Patent Number: 9595345
Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit…

Resistance-based memory with auxiliary redundancy information

Granted: March 14, 2017
Patent Number: 9595353
A data storage device includes a resistance-based memory. A method includes storing a codeword into a first set of storage elements of the resistance-based memory. The codeword represents data to be stored, and the codeword includes first redundancy information associated with the data. The method further includes storing auxiliary redundancy information into a second set of storage elements of the resistance-based memory. The auxiliary redundancy information is associated with the data.…

Floating gate separation in NAND flash memory

Granted: March 14, 2017
Patent Number: 9595444
A method of forming a NAND flash memory includes anisotropically etching trenches of a gate stack down to an intermediate level in a floating gate polysilicon layer, leaving remaining portions of the floating gate polysilicon over the gate dielectric layer. Subsequently, forming a protective layer along exposed sides of the trenches. Then, electrically separating individual floating gates by a selective process that is directed to the remaining portions of the floating gate polysilicon…

Semiconductor device including electromagnetic absorption and shielding

Granted: March 14, 2017
Patent Number: 9595454
A semiconductor device is disclosed including material for absorbing EMI and/or RFI The device includes a substrate (202), one or more semiconductor die (224,225), and molding compound around the one or more semiconductor die (224,225). The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer (210) on the substrate (202). The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing…

Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines

Granted: March 14, 2017
Patent Number: 9595566
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of…

Semiconductor memory device having unequal pitch vertical channel transistors employed as selection transistors and method for programming the same

Granted: March 14, 2017
Patent Number: 9595568
A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate. The transistor bodies may have an unequal pitch and a common height. Some of the transistor bodies can be misaligned with the vertical bit lines to fit the transistors to the stack. A method for programming the…