Sandisk Patent Grants

System and method for managing data in a memory device

Granted: June 27, 2017
Patent Number: 9690491
A non-volatile memory system may have a group of non-volatile memory cells having a plurality of predetermined portions, where each predetermined portion is associated with an open host write block of a different host data type than each other predetermined portion. A host data router directs received data from a host to an appropriate predetermined portion based on a determined data type. A maintenance data router, based on predetermined minimum capacity overprovisioning targets for…

Delayed automation to maximize the utilization of read and write cache

Granted: June 27, 2017
Patent Number: 9690515
A storage module may include a non-volatile memory module and a controller that communicates with the non-volatile memory module using a communications bus. In response to receipt of a host command, the controller may generate one or more sets of context commands for communication of data on the communications bus between the controller and an area of memory. The controller may execute the sets of context commands in a cache sequence. During execution of the context commands in the cache…

Dynamic host command rejection

Granted: June 27, 2017
Patent Number: 9690518
A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Apparatus, system, and method for an address translation layer

Granted: June 27, 2017
Patent Number: 9690694
An apparatus, system, and method are disclosed for storage address translation. The method includes storing, in volatile memory, a plurality of logical-to-physical mapping entries for a non-volatile recording device. The method includes persisting a logical-to-physical mapping entry from the volatile memory to recording media of the non-volatile recording device. The logical-to-physical mapping entry may be selected for persisting based on a mapping policy indicated by a client. The…

Adaptive operation of 3D memory

Granted: June 27, 2017
Patent Number: 9691473
A three dimensional nonvolatile memory system includes a sensing unit configured to sense bit line current and/or voltage for bit lines of a plurality of separately-selectable portions of a block and to compare respective results with a reference and an adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions in response to the comparing of respective results with the reference.

Storage system and method for marginal write-abort detection using a memory parameter change

Granted: June 27, 2017
Patent Number: 9691485
A storage system and method for marginal write-abort detection using a memory parameter change is provided. In one embodiment, a method for detecting a write abort is provided that is performed in a storage system having a memory. The method comprises reading a lower page in memory; determining if any data is written in the lower page; and in response to determining that no data is written in the lower page: increasing source voltage for memory cells in the lower page; re-reading the…

Multiheight contact via structures for a multilevel interconnect structure

Granted: June 27, 2017
Patent Number: 9691778
Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via…

Vertical resistor in 3D memory device with two-tier stack

Granted: June 27, 2017
Patent Number: 9691781
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends…

Monolithic three dimensional NAND strings and methods of fabrication thereof

Granted: June 27, 2017
Patent Number: 9691884
Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening,…

Method and system for facilitating fast wake-up of a flash memory system

Granted: June 20, 2017
Patent Number: RE46446
Methods, systems and computer-readable code for maintaining flash data structures in accordance with events of a flash memory system are disclosed. Both an events log as well as at least one flash management table are maintained in flash memory. For at least one point in time, a most recently stored flash memory table is indicative of an earlier state of the flash memory system, while at least one event that is more recent than the earlier state is stored in the events log. During…

Reference voltage generator for temperature sensor with trimming capability at two temperatures

Granted: June 20, 2017
Patent Number: 9683904
A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital…

Single input/output cell with multiple bond pads and/or transmitters

Granted: June 20, 2017
Patent Number: 9684474
A storage module may include a controller configured to communicate with a memory having a plurality of memory dies. The controller may include a plurality of bond pads, where each bond pad is configured to communicate a same type of memory signal, and where each bond pad is electrically connected to at least one but less than all of the plurality of memory dies. A core of the controller may identify a memory die that it wants to communicate a memory signal and an associated bond pad…

Method of forming 3D vertical NAND with III-V channel

Granted: June 20, 2017
Patent Number: 9685454
Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better…

Reversible resistivity memory with crystalline silicon bit line

Granted: June 20, 2017
Patent Number: 9685484
Technology is described for reversible resistivity memory having a crystalline silicon bit line. In one aspect, a memory structure comprises a hollow pillar of crystalline silicon inside of reversible resistivity material. The crystalline silicon may serve as a bit line. The memory structure may further comprise conductive material that forms word lines coupled to the outer surface of the reversible resistivity material. A memory cell comprises a portion of the reversible resistivity…

Apparatus and method for controlling wireless power transfer to mobile devices

Granted: June 20, 2017
Patent Number: 9685791
A system for controlling wireless power transfer to mobile devices is disclosed. The system includes a power transmitter configured to transmit power via a wireless coupling to the mobile devices. Each of the mobile devices includes a power receiver configured to receive the power from the power transmitter via the wireless coupling with the power transmitter. Each power receiver is configured to transmit control data modulated with a spreading code via the wireless coupling to the power…

Three dimensional hexagonal matrix memory array

Granted: June 13, 2017
Patent Number: RE46435
A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Memory system and method for power management for reducing a variable credit value by a computed consumed energy value for each corresponding updated cycle

Granted: June 13, 2017
Patent Number: 9678558
In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time…

Systems and methods for performing an adaptive sustain write in a memory system

Granted: June 13, 2017
Patent Number: 9678684
Systems and methods for performing an adaptive sustain write are disclosed. In one implementation, a controller of a non-volatile memory that is coupled with a host system monitors a rate at which the host system sends user data to the non-volatile memory system for storage and determines that the rate at which the host system sends user data to the non-volatile memory system for storage exceeds a threshold. The controller stores a first portion of the user data in one or more user…

Storage module and method for on-chip copy gather

Granted: June 13, 2017
Patent Number: 9678832
A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After…

Hybrid checkpointed memory

Granted: June 13, 2017
Patent Number: 9678863
Apparatuses, systems, methods, and computer program products are disclosed for hybrid checkpointed memory. A method includes referencing data of a range of virtual memory of a host. The referenced data is already stored by a non-volatile medium. A method includes writing, to a non-volatile medium, data of a range of virtual memory that is not stored by the non-volatile medium. A method includes providing access to data of a range of virtual memory from a non-volatile medium using a…