Memory device using a multilayer ferroelectric stack and method of forming the same
Granted: April 23, 2024
Patent Number:
11968839
A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.
Three-dimensional memory device including discrete charge storage elements with laterally-protruding profiles and methods of making thereof
Granted: April 23, 2024
Patent Number:
11968834
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally…
Three-dimensional memory device with replacement select gate electrodes and methods of manufacturing the same
Granted: April 23, 2024
Patent Number:
11968827
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by…
Three-dimensional memory device with metal-barrier-metal word lines and methods of making the same
Granted: April 23, 2024
Patent Number:
11968826
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the…
Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same
Granted: April 23, 2024
Patent Number:
11968825
A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures…
Field effect transistors with gate fins and method of making the same
Granted: April 23, 2024
Patent Number:
11967626
A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.
Mixing normal and reverse order programming in NAND memory devices
Granted: April 23, 2024
Patent Number:
11967382
The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further…
Non-volatile storage system with program execution decoupled from dataload
Granted: April 23, 2024
Patent Number:
11966621
Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct…
Three-dimensional memory device with vertical field effect transistors and method of making thereof
Granted: April 16, 2024
Patent Number:
11963352
A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect…
Three-dimensional memory device with dielectric or semiconductor wall support structures and method of forming the same
Granted: April 16, 2024
Patent Number:
11963354
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through each layer of the alternating stack; memory opening fill structures located in the memory openings, and a perforated wall structure including lateral openings at levels of the insulating layers.
Memory device that is optimized for operation at different temperatures
Granted: April 16, 2024
Patent Number:
11961573
A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line…
Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain side select gate technology
Granted: April 16, 2024
Patent Number:
11961572
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells…
Balancing peak power with programming speed in non-volatile memory
Granted: April 16, 2024
Patent Number:
11961563
Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc…
Memory cell group read with compensation for different programming speeds
Granted: April 9, 2024
Patent Number:
11955184
Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the…
Adaptive pre-programming
Granted: April 9, 2024
Patent Number:
11955182
Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane…
Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same
Granted: April 2, 2024
Patent Number:
11948902
A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die…
Implementation of deep neural networks for testing and quality control in the production of memory devices
Granted: April 2, 2024
Patent Number:
11947890
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural…
Three-dimensional memory device and method of making thereof using double pitch word line formation
Granted: March 26, 2024
Patent Number:
11942429
A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are…
Variable bit line bias for nonvolatile memory
Granted: March 26, 2024
Patent Number:
11942157
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a…
Free flow data path architectures
Granted: March 19, 2024
Patent Number:
11935622
A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by…
