Sandisk Patent Grants

Storage device blister tray

Granted: May 23, 2017
Patent Number: D787309

Storage device blister tray

Granted: May 23, 2017
Patent Number: D787310

Storage module and host device for storage module defragmentation

Granted: May 23, 2017
Patent Number: 9658777
A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the…

Systems and methods for immediate physical erasure of data stored in a memory system in response to a user command

Granted: May 23, 2017
Patent Number: 9658788
Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further…

Storage module and method for optimized power utilization

Granted: May 23, 2017
Patent Number: 9658789
A storage module and method are provided for optimized power utilization. In one embodiment, a storage module is provided comprising a storage controller and a plurality of memory dies in communication with the storage controller. The storage controller determines if sufficient power is available to perform an operation on one of the memory dies. In response to determining that sufficient power is not available to perform the operation on one of the memory dies, the storage controller…

Memory system and method for power-based operation scheduling

Granted: May 23, 2017
Patent Number: 9658790
A memory system and method for power-based operation scheduling are provided. In one embodiment, a memory system begins to perform a plurality of operations in an order in which they are stored in a queue. Before performing a next operation in the queue, the memory system determines whether the power consumed by performing the next operation would exceed a maximum power threshold. In response to determining that the power consumed would exceed the maximum power threshold, the memory…

End of life prediction based on memory wear

Granted: May 23, 2017
Patent Number: 9658800
A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear,…

Systems and methods for managing data input/output operations

Granted: May 23, 2017
Patent Number: 9658957
Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache…

Systems and methods of write cache flushing

Granted: May 23, 2017
Patent Number: 9658966
A data storage device includes a write cache, a non-volatile memory, and a controller coupled to the write cache and to the non-volatile memory. The controller is configured to, responsive to receiving a command to flush particular data from the write cache, attempt to fill a write block of data using the particular data and pending data obtained after receipt of the command.

System and method for memory integrated circuit chip write abort indication

Granted: May 23, 2017
Patent Number: 9659619
Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being…

Techniques for programming of select gates in NAND memory

Granted: May 23, 2017
Patent Number: 9659656
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set…

Dynamic memory recovery at the sub-block level

Granted: May 23, 2017
Patent Number: 9659666
A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to…

Three-dimensional memory structures with low source line resistance

Granted: May 23, 2017
Patent Number: 9659866
Dielectric pedestal structures embedded in a sacrificial material layer is formed between a substrate and an alternating stack of insulating layers and spacer material layers. After memory openings are formed through the alternating layer, a cavity is formed by removal of the sacrificial material layer selective to the dielectric pedestal structures. A memory film, a semiconductor channel layer, and a dielectric core are sequentially formed in the volume including the cavity and the…

System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers

Granted: May 23, 2017
Patent Number: 9659882
A system, method and apparatus for making a semiconductor die includes forming multiple semiconductor devices in a respective portion of a semiconductor wafer. An electrical interconnect structure is formed over the semiconductor devices and provide electrical connections to the semiconductor devices. The electrical interconnect structure including one or more metallization layers. Each of the metallization layers includes conductive lines. At least one portion of at least one of the…

Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure

Granted: May 23, 2017
Patent Number: 9659955
A method of forming a device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, and forming an aluminum oxide layer on sidewall surfaces of the sacrificial material layers and on sidewall surfaces of the insulating layers around the memory opening. First aluminum oxide portions of the aluminum oxide layer are located on sidewall surfaces of the sacrificial material…

Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation

Granted: May 23, 2017
Patent Number: 9659956
A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer,…

Delay compensation

Granted: May 23, 2017
Patent Number: 9660656
Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is…

Sub-block garbage collection

Granted: May 16, 2017
Patent Number: 9652381
Systems, methods and/or devices are used to enable garbage collection of a sub-block of an individually erasable block of a storage medium in a storage device. In one aspect, the method includes determining a first trigger parameter in accordance with one or more operating conditions of a first sub-block of an erase block in the storage medium, and determining a second trigger parameter in accordance with one or more operating conditions of a second sub-block of the erase block in the…

Atomic non-volatile memory data transfer

Granted: May 16, 2017
Patent Number: 9652415
The various implementations described herein include systems, methods and/or devices used to transfer data within a storage device. In one aspect, a method includes reading data from a first non-volatile memory device to a shared bus, where the shared bus couples the first non-volatile memory device to a second non-volatile memory device and to the controller, and where the first non-volatile memory device is on a first die and the second non-volatile memory device is on a second die,…

Digital ramp rate control for charge pumps

Granted: May 16, 2017
Patent Number: 9653126
Methods for controlling a ramp rate of an output voltage derived from one or more charge pumps and reducing variation in the ramp rate due to process, voltage, and temperature (PVT) variations are described. In some embodiments, the ramp rate of the output voltage from one or more charge pumps may be controlled using a ramp rate control circuit that uses a digital counter to adjust (or step up) the output voltage from the one or more charge pumps based on a ramp rate schedule. The ramp…