Sandisk Patent Grants

System and method of updating metablocks associated with multiple memory dies

Granted: April 25, 2017
Patent Number: 9632712
A method includes, in a data storage device that includes a non-volatile memory having multiple memory dies, determining whether one or more metablocks are metablock update candidates based on relinking metrics corresponding to the one or more metablocks. Each memory die includes multiple blocks of storage elements, and metablocks are formed through linking of blocks from the multiple memory dies. The method also includes comparing a number of the metablock update candidates to a…

Method and computing device for encrypting data stored in swap memory

Granted: April 25, 2017
Patent Number: 9633233
The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area.

Accelerated physical secure erase

Granted: April 25, 2017
Patent Number: 9633738
A storage system includes a controller that is configured to make host data inaccessible. To do so, the controller may control power control circuitry to supply pulses to storage locations storing host data. The pulses may include flash write pulses but no erase pulses, or a combination of flash write pulses and erase pulses. If erase pulses are supplied, the number of the erase pulses may be less than the number supplied for performance of a default erase operation.

Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

Granted: April 25, 2017
Patent Number: 9633742
In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety.…

System and method of managing tags associated with read voltages

Granted: April 25, 2017
Patent Number: 9633749
A data storage device includes a controller coupled to a non-volatile memory. The non-volatile memory is configured to store multiple tags that include a first tag and a second tag. The controller is configured to determine one or more candidate values associated with a candidate tag. The one or more candidate values may be determined based on an operation applied to the first tag and the second tag. The controller is further be configured to cause the non-volatile memory to remove the…

3D NAND with oxide semiconductor channel

Granted: April 25, 2017
Patent Number: 9634097
Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline…

System and method for memory command queue management and configurable memory status checking

Granted: April 18, 2017
Patent Number: 9626106
Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such…

Method and system for using a ROM patch

Granted: April 18, 2017
Patent Number: 9626179
A method and system for using a ROM patch are provided. In one embodiment, a computing device obtains an original assembly code and a modified assembly code which is a modified version of the original assembly code, the original assembly code being used for an executable code which is stored in a ROM of a device. The computing device compares the original assembly code and the modified assembly code to identify difference(s) in the modified assembly code with respect to the original…

Hardware and firmware paths for performing memory read processes

Granted: April 18, 2017
Patent Number: 9626286
A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules. The firmware module performs the processes when the hardware modules are not able to successfully…

Metalblock relinking to physical blocks of semiconductor memory in adaptive wear leveling based on health

Granted: April 18, 2017
Patent Number: 9626289
Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks…

Storage module, host, and method for securing data with application information

Granted: April 18, 2017
Patent Number: 9626304
A storage module, host, and method for securing data with application information are disclosed. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to store data and information about an application that generated the data and allow the data to be read only if information about an application attempting to read the data matches the information about the application that generated the data. Other embodiments are possible, and…

Storage region mapping for a data storage device

Granted: April 18, 2017
Patent Number: 9626312
A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write data to a first meta-block if a storage size associated with a first group of data storage dies associated with a first priority is greater than or equal to a threshold storage size. The first meta-block includes a respective block of each data storage die of the first group. The controller is further configured to write the data to a…

Conditional updates for reducing frequency of data modification operations

Granted: April 18, 2017
Patent Number: 9626399
A computer system detects a request, from a requestor, to access a first data object stored in a tiered data structure that includes internal nodes and leaf nodes. In response to detecting the request to access the first data object, the computer system retrieves a leaf node that includes the first data object and locks the leaf node that includes the first data object. While the leaf node that includes the first data object is locked, the computer system transmits, to the requestor, a…

Compaction of information in tiered data structure

Granted: April 18, 2017
Patent Number: 9626400
A computer system detects a request to access a first data object stored in a tiered data structure, that includes internal nodes and leaf nodes, where data objects in the leaf nodes include unique key information and corresponding values, and the first data object is uniquely identified by a first key. In response to detecting the request to access the first data object, the computer system retrieves a leaf node that includes the first data object and identifies the first data object in…

Interleaved grouped word lines for three dimensional non-volatile storage

Granted: April 18, 2017
Patent Number: 9627009
A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three…

Programming techniques for non-volatile memories with charge trapping layers

Granted: April 18, 2017
Patent Number: 9627046
Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.

Height reduction in memory periphery

Granted: April 18, 2017
Patent Number: 9627393
A NAND flash memory has word lines in a memory array area and contact pads and lead lines in a word line hookup area, each of the word lines connected to a corresponding contact pad by a lead line. The word lines in the memory array area have a first height and low-profile areas of lead lines in the word line hookup area have a second height that is less than the first height.

Enhanced channel mobility three-dimensional memory structure and method of making thereof

Granted: April 18, 2017
Patent Number: 9627395
A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel,…

Three-dimensional memory device with metal and silicide control gates

Granted: April 18, 2017
Patent Number: 9627399
An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended…

Multilevel memory stack structure employing support pillar structures

Granted: April 18, 2017
Patent Number: 9627403
A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second…