CONTACT CONFIGURATION FOR UNDERTAKING TESTS ON CIRCUIT BOARD
Granted: August 21, 2014
Application Number:
20140235106
An electronic structure (for example a reliability board or a cycling control module) has a body including a body portion insertable into a connector. A plurality of contact structures are provided on a side of the body portion, each contact structure comprising a first contact and a second contact spaced from the first contact, with the first and second contacts of each contact structure being aligned in the direction of insertion of the body portion into the connector. A corresponding…
OPERATING SYSTEM BASED DRAM AND FLASH MANAGEMENT
Granted: August 14, 2014
Application Number:
20140229661
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
DATA PATTERN ANALYSIS (as amended)
Granted: August 14, 2014
Application Number:
20140229178
A method for real-time data-pattern analysis. The method includes receiving and queuing at least one data-pattern analysis request by a data-pattern analysis unit controller. At least one data stream portion is also received and stored by the data-pattern analysis unit controller, each data stream portion corresponding to a received data-pattern analysis request. Next, a received data-pattern analysis request is selected by the data-pattern analysis unit controller along with a…
FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTS
Granted: August 14, 2014
Application Number:
20140225177
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the…
MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS
Granted: August 7, 2014
Application Number:
20140223054
A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
SEMICONDUCTOR MEMORY DEVICE
Granted: August 7, 2014
Application Number:
20140219035
Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the…
NON-VOLATILE MEMORY DEVICE
Granted: August 7, 2014
Application Number:
20140219018
A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits.
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
Granted: July 31, 2014
Application Number:
20140208554
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion…
CONVEX SHAPED THIN-FILM TRANSISTOR DEVICE
Granted: July 31, 2014
Application Number:
20140209991
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the…
Non-Volatile Memory With Silicided Bit Line Contacts
Granted: July 31, 2014
Application Number:
20140209993
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density…
Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions
Granted: July 31, 2014
Application Number:
20140210012
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly…
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
Granted: July 31, 2014
Application Number:
20140215111
Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
Control Circuit of Step-Down DC-DC Converter, Control Circuit of Step-Up DC-DC Converter and Step-Up/Step-Down DC-DC Converter
Granted: July 24, 2014
Application Number:
20140203792
A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit 11 of a current mode step-down DC-DC converter 1 includes a slope compensation circuit SC and an offset circuit IF1. The slope compensation circuit SC adds an increase gradient m2 due to slope compensation to an increase gradient of a coil current waveform Vsense in a range wherein an ON period Ton of a switch SW1 exceeds ½ of an operating cycle T. An offset circuit IF1 applies an…
SWITCHABLE MEMORY DIODES BASED ON FERROELECTRIC/CONUUGATED POLYMER HETEROSTRUCTURES AND/OR THEIR COMPOSITES
Granted: July 24, 2014
Application Number:
20140203263
An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and…
DEBUG CONTROL CIRCUIT
Granted: July 17, 2014
Application Number:
20140201403
An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a…
SELF-ALIGNED DOUBLE PATTERNING FOR MEMORY AND OTHER MICROELECTRONIC DEVICES
Granted: July 10, 2014
Application Number:
20140191308
A semiconductor device is provided. The semiconductor device includes a microelectronic layer, a first mask layer formed on the microelectronic layer having first features separated by first openings, and a second mask layer formed on the first mask layer having second features that are separated by second openings. Each second feature is centrally located on a respective one of the first features. A length each second feature in a dimension is substantially equal to a length of a…
Distributed Speech Recognition System
Granted: July 10, 2014
Application Number:
20140195233
Embodiments of the present invention include an apparatus, method, and system for speech recognition of a voice command. The method can include receiving data representing a voice command, generating a list of targets based on the state information of each target within the system, and selecting a target from the list of targets, based on the voice command.
Buried Hard Mask for Embedded Semiconductor Device Patterning
Granted: July 10, 2014
Application Number:
20140193972
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second…
PROGRAMMABLE AND FLEXIBLE REFERENCE CELL SELECTION METHOD FOR MEMORY DEVICES
Granted: July 10, 2014
Application Number:
20140192581
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more…
Multi-Chip Package Assembly with Improved Bond Wire Separation
Granted: July 10, 2014
Application Number:
20140191417
A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to…
