Spacer design to prevent trapped electrons
Granted: September 16, 2014
Patent Number:
8836012
Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
Method to improve charge trap flash memory core cell performance and reliability
Granted: September 16, 2014
Patent Number:
8835277
A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
Inter-bus communication interface device and data security device
Granted: September 9, 2014
Patent Number:
8832460
There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the…
Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory
Granted: September 9, 2014
Patent Number:
8832408
A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
A/D converter
Granted: September 9, 2014
Patent Number:
8830097
An arithmetic operation circuit provided in a delta-sigma modulator of a delta-sigma A/D converter includes two reference capacitors which are respectively provided at a positive side input node and a negative side input node of an operational amplifier. When a signal corresponding to an output of the modulator is added or subtracted to or from an input signal, the amount of charge added to the input node of the operational amplifier is made to be always the same regardless of the…
Metal-insulator-metal (MIM) device and method of formation thereof
Granted: September 9, 2014
Patent Number:
8828837
In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer.…
High voltage gate formation
Granted: September 2, 2014
Patent Number:
8822289
Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this…
Field upgradable firmware for electronic devices
Granted: September 2, 2014
Patent Number:
8825920
An electronic device includes an input/output (I/O) interface and a plurality of memory elements comprising a non-volatile memory portion for storing a default firmware and a working memory portion having a firmware area. The device also includes a controller coupled to the I/O interface and the memory elements, where the controller is configured for operating the memory elements, according to the firmware area, and for monitoring the I/O interface. In the device, the controller is also…
Packet communication device for communicating packet to be transferred through packet communication which is time-managed in constant cycle and packet communication method thereof
Granted: September 2, 2014
Patent Number:
8824469
A packet communication device for communicating a packet to be transferred in constant cycle, comprising one of a logic inversion section configured to invert a logical value with respect to at least one bit included in a first string of bits included in a first packet; and a register section configured to store another string of bits having a logical value different from a given logical value of the first string of bits; and a selector section configured to select one of the first…
Control circuit, electronic device, and method for controlling power supply
Granted: September 2, 2014
Patent Number:
8823344
A control circuit arranged in a power supply including first and second switches to control an output voltage of the power supply. The control circuit includes a first control circuit that switches the first and second switches in a complementary manner in accordance with a comparison result of a first reference voltage and a feedback voltage corresponding to the output voltage of the power supply. A first comparison circuit compares the output voltage or feedback voltage with a second…
Semiconductor device and reset control method in semiconductor device
Granted: August 26, 2014
Patent Number:
8819401
Reset request from external are held at a reset request holding unit having holding units connected in series; a reset switching unit performs a logical product operation of all of outputs of the holding units to set it as an asynchronous reset request, setting an output of the holding unit at a final stage of the holding units as a synchronous reset request, performing a logical product operation of the asynchronous reset request and the synchronous reset request, and outputs an…
Host/client system having a scalable serial bus interface
Granted: August 26, 2014
Patent Number:
8819326
According to one exemplary embodiment, a host/client system includes a host module, which includes a CPU coupled to a system bridge. The host/client system further includes at least one client having an integrated interface, where the integrated interface is coupled to the system bridge through a scalable serial bus. The system bridge and the integrated interface enable high bandwidth communication between the CPU and the at least one client through the scalable serial bus, thereby…
Real-time data pattern analysis system and method of operation thereof
Granted: August 26, 2014
Patent Number:
8818802
A method for real-time data-pattern analysis. The method includes receiving and queuing at least one data-pattern analysis request by a data-pattern analysis unit controller. At least one data stream portion is also received and stored by the data-pattern analysis unit controller, each data stream portion corresponding to a received data-pattern analysis request. Next, a received data-pattern analysis request is selected by the data-pattern analysis unit controller along with a…
Process charging protection for split gate charge trapping flash
Granted: August 26, 2014
Patent Number:
8816438
A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region…
Semiconductor device and method of manufacturing the same and semiconductor manufacturing device
Granted: August 26, 2014
Patent Number:
8815652
The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality…
Integrated circuit with metal and semi-conducting gate
Granted: August 26, 2014
Patent Number:
8815727
A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
Storage device, control method of storage device, and control method of storage control device
Granted: August 19, 2014
Patent Number:
8811107
Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn…
Memory cell system with multiple nitride layers
Granted: August 19, 2014
Patent Number:
8809936
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
Patterned dummy wafers loading in batch type CVD
Granted: August 19, 2014
Patent Number:
8809206
A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the…
Continuous read burst support at high clock rates
Granted: August 12, 2014
Patent Number:
8806071
A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output…
