ENERGY-EFFICIENT SFQ LOGIC BIASING TECHNIQUE
Granted: May 12, 2022
Application Number:
20220149841
Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being…
AGING-RESISTANT SCHMITT RECEIVER CIRCUIT
Granted: April 21, 2022
Application Number:
20220123738
A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.
PERFORMING HARDWARE DESCRIPTION LANGUAGE TRANSFORMATIONS
Granted: April 7, 2022
Application Number:
20220108056
Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be…
POWER HARVESTING FOR INTEGRATED CIRCUITS
Granted: March 3, 2022
Application Number:
20220069007
Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed…
Formal Gated Clock Conversion for Field Programmable Gate Array (FPGA) Synthesis
Granted: March 3, 2022
Application Number:
20220067251
Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes…
ADAPTIVE SCHEDULING WITH DYNAMIC PARTITION-LOAD BALANCING FOR FAST PARTITION COMPILATION
Granted: March 3, 2022
Application Number:
20220066824
Disclosed herein are method, system, and computer-readable storage-medium embodiments of adaptive scheduling with dynamic partition-load balancing for fast partition compilation. An embodiment includes detecting, by at least one processor, an available hardware-resource amount available to be used by an electronic design automation (EDA) process via a plurality of computing elements, with respect to a design specification, and analyzing the design specification, to generate an estimate…
GLOBAL MISTRACKING ANALYSIS IN INTEGRATED CIRCUIT DESIGN
Granted: February 17, 2022
Application Number:
20220050947
For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.
SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET)
Granted: January 20, 2022
Application Number:
20220020647
A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a…
EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET)
Granted: January 20, 2022
Application Number:
20220020646
A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and…
INCREMENTAL ROUTING BASED PIN ASSIGNMENT
Granted: January 6, 2022
Application Number:
20220004693
The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design…
SEGREGATING DEFECTS BASED ON COMPUTER-AIDED DESIGN (CAD) IDENTIFIERS ASSOCIATED WITH THE DEFECTS
Granted: December 30, 2021
Application Number:
20210406441
For each defect in a set of defects, the defect may be associated with a defect attribute constructed from a set of computer-aided design (CAD) identifiers associated with polygons in an integrated circuit (IC) design that overlap with a defect area of the defect. Next, the set of defects may be segregated into defect groups based on the associated defect attributes. The defect groups may be used to perform additional processing on the set of defects.
Phase-Aware DDR Command Dynamic Scheduling
Granted: December 2, 2021
Application Number:
20210375341
A method for performing phase aware dynamic scheduling of a plurality of double data rate (DDR) commands includes determining a ratio of a frequency of DDR controller clock to a frequency of a DDR clock. The method includes determining a number of clock cycles of the DDR clock required for each DDR command of the plurality of DDR commands. The method includes, based on the ratio of the frequency of the DDR controller clock to the frequency of the DDR clock and the number of clock cycles…
FINDING EQUIVALENT CLASSES OF HARD DEFECTS IN STACKED MOSFET ARRAYS
Granted: December 2, 2021
Application Number:
20210374313
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the…
DEFECT WEIGH FORMULAS FOR ANALOG DEFECT SIMULATION
Granted: November 11, 2021
Application Number:
20210350058
A method, apparatus, and/or computer program product can performing an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling…
DETERMINING AND VERIFYING METASTABILITY IN CLOCK DOMAIN CROSSINGS
Granted: November 11, 2021
Application Number:
20210350053
The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination…
Interconnect Repeater Planning and Implementation Flow for Abutting Designs
Granted: November 11, 2021
Application Number:
20210349845
A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes,…
Power Estimation System
Granted: October 28, 2021
Application Number:
20210333853
A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.
FAST AND SCALABLE METHODOLOGY FOR ANALOG DEFECT DETECTABILITY ANALYSIS
Granted: October 21, 2021
Application Number:
20210326227
A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit…
METHOD FOR FINDING EQUIVALENT CLASSES OF HARD DEFECTS IN STACKED MOSFET ARRAYS
Granted: October 7, 2021
Application Number:
20210312113
In modern VLSI technology, often, stacked arrays of smaller sized MOSFETs are used to achieve the desired width and length of a design MOSFET. In analog defect simulation, each physical transistor can contribute to the circuit's defect universe and this can directly lead to tremendous increase in defect simulation time. Here we propose a method of finding equivalent defects in the context of stacked MOSFET arrays that can lead to significant reduction in defect simulation effort and yet…
MACHINE LEARNING-BASED PREDICTION OF METRICS AT EARLY-STAGE CIRCUIT DESIGN
Granted: September 16, 2021
Application Number:
20210287120
When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML)…
