Synopsys Patent Grants

Method for ranking fault-test pairs based on waveform statistics in a mutation-based test program evaluation system

Granted: May 23, 2017
Patent Number: 9658947
Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a…

X-propagation in emulation

Granted: May 23, 2017
Patent Number: 9659118
Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a…

Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design

Granted: May 16, 2017
Patent Number: 9652573
Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-gates as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-gate objects. These new objects can enable rapid access and preservation of wide-gates, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Image processing method

Granted: May 16, 2017
Patent Number: 9652889
A computer-implemented image processing technique for selectively recovering the features of an original CAD model after the original CAD model has been converted to a digitized image and a new CAD model generated from the digitized image. The original boundary representation provides a template to transform the representation through processing under governance of a programmed processor so as to recover accuracy and reintroduce feature edges and feature corners as well as other detailed…

3D resist profile aware etch-bias model

Granted: May 9, 2017
Patent Number: 9646127
Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

Notch detection and correction in mask design data

Granted: May 9, 2017
Patent Number: 9646129
Mask data is analyzed for the presence of a notch. A notch candidate on a polygon boundary of mask data is defined as a plurality of line segments that includes an initial line segment, a final line segment and at least two line segments therebetween. The initial and final line segments define adjacent edges of the notch candidate. A direction of each line segment is a direction of travel from the initial line segment to the final line segment.

Two-way parity error detection for advanced encryption standard engines

Granted: May 9, 2017
Patent Number: 9646175
A method of improving the operation of a processor executing a cryptographic process, by automatically detecting faults during both encryption and decryption operations by the cryptographic process, comprises segmenting the data to be encrypted and encrypting the data segments using a complex non-linear algorithm that can lead to faults; computing an output parity bit from a selected step of the algorithm for a selected data segment, based on the input value of that segment; comparing…

N-channel and P-channel end-to-end finFET cell architecture

Granted: May 9, 2017
Patent Number: 9646966
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a…

Network-based testing service and method of testing in a network

Granted: May 2, 2017
Patent Number: 9639456
A network-based testing method and service integrated with a tool that publishes one or more tagged test cases with tags being executable to reproduce a sequence of events for a system under test, SUT, caused by an original test case. The method is performed in a network and is intended for testing software or hardware by first creating an original test case for a system under test, SUT, and performing a sequence of events for the original test case for testing it. The tested case is…

Goal-based cell partitioning in the presence of obstacles

Granted: May 2, 2017
Patent Number: 9639648
Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions.

Sequential structure extraction by functional specification

Granted: April 25, 2017
Patent Number: 9633154
A method and apparatus for structure analysis of a circuit design are described. In one exemplary embodiment, a functional specification of a circuit design is received, where the functional specification is defined based on a behavior layer abstraction. In addition, design codes for the circuit design are received, wherein in each design code of the design codes is defined based on the behavior layer abstraction. Furthermore, the design codes are searched, which is performed in the…

Assertion extraction from design and its signal traces

Granted: April 18, 2017
Patent Number: 9626468
Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using…

Generating a circuit description for a multi-die field-programmable gate array

Granted: April 18, 2017
Patent Number: 9626470
A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding…

Prioritization of tests of computer program code

Granted: April 4, 2017
Patent Number: 9612943
A method is provided to prioritize testing of computer program code comprising: determining first test coverages of items within a first source code version for multiple tests; storing in a non-transitory storage device, a first history that indicates the determined first test coverages of the items within the first source code version; identifying occurrences of the items within a second source code version; determining first weights associated with tests, wherein a respective weight…

Buffer chain management for alleviating routing congestion

Granted: April 4, 2017
Patent Number: 9613176
Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage,…

Method and apparatus for debugging HDL design code and test program code

Granted: March 21, 2017
Patent Number: 9600398
Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values…

Floating gate non-volatile memory bit cell

Granted: March 21, 2017
Patent Number: 9601203
A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes…

Data storage element and signal processing method

Granted: March 21, 2017
Patent Number: 9602085
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input…

Optimization of parasitic capacitance extraction using statistical variance reduction technique

Granted: March 14, 2017
Patent Number: 9594727
A method for performing parasitic capacitance extraction of an integrated circuit (IC) design includes: defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; performing an initial plurality of random walks from each region using a Monte Carlo field solver; and dynamically allocating an additional plurality of random walks among the plurality of regions, wherein the allocation is based on statistical errors…

DRC-based hotspot detection considering edge tolerance and incomplete specification

Granted: March 14, 2017
Patent Number: 9594867
A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification (“don't care”) regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted…