Synopsys Patent Grants

Method and apparatus for debugging HDL design code and test program code

Granted: March 21, 2017
Patent Number: 9600398
Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values…

Floating gate non-volatile memory bit cell

Granted: March 21, 2017
Patent Number: 9601203
A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes…

Data storage element and signal processing method

Granted: March 21, 2017
Patent Number: 9602085
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input…

Optimization of parasitic capacitance extraction using statistical variance reduction technique

Granted: March 14, 2017
Patent Number: 9594727
A method for performing parasitic capacitance extraction of an integrated circuit (IC) design includes: defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; performing an initial plurality of random walks from each region using a Monte Carlo field solver; and dynamically allocating an additional plurality of random walks among the plurality of regions, wherein the allocation is based on statistical errors…

DRC-based hotspot detection considering edge tolerance and incomplete specification

Granted: March 14, 2017
Patent Number: 9594867
A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification (“don't care”) regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted…

Scheme for masking output of scan chains in test circuit

Granted: March 7, 2017
Patent Number: 9588179
A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If…

Method and system for reproducing prototyping failures in emulation

Granted: March 7, 2017
Patent Number: 9589084
A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.

Dynamically loaded system-level simulation

Granted: February 28, 2017
Patent Number: 9582623
A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to the component library information are loaded based on the component library…

Sensing scheme for high speed memory circuits with single ended sensing

Granted: February 28, 2017
Patent Number: 9583208
A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as…

Method for managing design files shared by multiple users and system thereof

Granted: February 21, 2017
Patent Number: 9575986
A method for managing design files shared by multiple users is provided. A plurality of design files are stored in a design library. A lock table is moved to a memory of a first computer when information of the lock table indicates that the design files were locked by a first process corresponding to a first user, wherein the memory is only accessible to performance of the first process. The lock table is moved from the memory to a common memory of the first computer when one design file…

Lithography aware leakage analysis

Granted: February 21, 2017
Patent Number: 9576098
A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the…

Identifying failure indicating scan test cells of a circuit-under-test

Granted: February 14, 2017
Patent Number: 9568550
A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at…

Processor branch cache with secondary branches

Granted: February 14, 2017
Patent Number: 9569220
A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch…

Delay-locked loop arrangement and method for operating a delay-locked loop circuit

Granted: February 14, 2017
Patent Number: 9571080
Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode…

Early content engine receiver synchronization

Granted: February 14, 2017
Patent Number: 9571473
An HDCP receiver device that receives frames from an HDCP transmitter device. The receiver device has a frame counter that is updated for each frame that is received from the transmitter device and that includes encrypted content, while the receiver device is in a pre-authorization mode. During the pre-authorization mode, the receiver device does not decrypt any received frame bearing encrypted content. While the receiver device waits to transition from the pre-authorization mode to a…

Memory tamper detection

Granted: February 7, 2017
Patent Number: 9563577
A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor. by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one implementation, each of the memory blocks has an authentication code, and the accessing of the memory blocks is disabled by disabling the untrusted…

Retiming a design for efficient parallel simulation

Granted: January 31, 2017
Patent Number: 9558306
An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that…

Determining a user-specified location in a graphical user interface of an electronic design automation tool

Granted: January 24, 2017
Patent Number: 9552450
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in _a circuit design layout in response to modifying the…

NVM device using FN tunneling with parallel powered source and drain

Granted: January 24, 2017
Patent Number: 9553207
A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The…

Efficient event detection

Granted: January 17, 2017
Patent Number: 9547040
Embodiments relate to the emulation of circuits, and detecting an event in a plurality of signals in an emulated circuit. A host system incorporates global event detection logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated global event detection logic. The global event detection logic divides one clock cycle of the DUT into multiple time periods. During each time period of the clock cycle, the emulator selects a different subset of signals from…