Synopsys Patent Grants

2D material super capacitors

Granted: August 15, 2017
Patent Number: 9735227
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide.…

Parameter extraction of DFT

Granted: August 8, 2017
Patent Number: 9727675
Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.

Graphical view and debug for coverage-point negative hint

Granted: August 8, 2017
Patent Number: 9727678
The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in…

Method and apparatus for floating or applying voltage to a well of an integrated circuit

Granted: August 8, 2017
Patent Number: 9728528
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the…

Area-delay-power efficient multibit flip-flop

Granted: August 8, 2017
Patent Number: 9729128
A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local…

Information theoretic caching for dynamic problem generation in constraint solving

Granted: August 1, 2017
Patent Number: 9720792
Computer-implemented techniques are disclosed for verifying circuit designs using dynamic problem generation. A device under test (DUT) is modeled as part of a test bench where the test bench is a random process. A set of constraints is solved to generate stimuli for the DUT. Problem generation is repeated numerous times throughout a verification process with problems and sub-problems being generated and solved. When a problem is solved, the problem structure can be stored in a cache.…

Method for wire widening in circuit routing system

Granted: August 1, 2017
Patent Number: 9721056
A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in…

System and method for netlist clock domain crossing verification

Granted: August 1, 2017
Patent Number: 9721057
A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The…

System and method for reactive initialization based formal verification of electronic logic design

Granted: August 1, 2017
Patent Number: 9721058
A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to…

Protection scheme for embedded code

Granted: July 25, 2017
Patent Number: 9715463
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a…

Identifying failure mechanisms based on a population of scan diagnostic reports

Granted: July 11, 2017
Patent Number: 9703658
Systems and techniques for identifying failure mechanisms based on a population of scan diagnostic reports is described. Given a population of scan diagnostic reports, a mixed membership model can be used for computing a topic distribution for each portion of each scan diagnostic report and a feature distribution for each topic. The failure mechanisms can be identified based on the topic distributions for the portions of the scan diagnostic reports and the feature distributions for the…

Techniques for creating and using a hierarchical data structure

Granted: July 4, 2017
Patent Number: 9697211
Techniques for creating and using a hierarchical data structure, in accordance with embodiments of the present invention include storing received data as records in a first level of the hierarchical data structure. One or more parameters for each block of records in the first level are summarized and stored in a second level of the hierarchical data structure. The techniques may also include querying a given level of a hierarchical data structure. One or more blocks of records one level…

Organization for virtual-flat expansion of physical data in physically-hierarchical IC designs

Granted: July 4, 2017
Patent Number: 9697313
In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate…

Identifying and using slices in an integrated circuit (IC) design

Granted: July 4, 2017
Patent Number: 9697314
Systems and techniques are described for designing an integrated circuit (IC). Some embodiments identify and preserve slices by using new objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such slice objects. These new objects can enable rapid access and preservation of slices, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Hardware accelerator test harness generation

Granted: June 27, 2017
Patent Number: 9690630
System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware…

Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design

Granted: June 27, 2017
Patent Number: 9690890
Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-buses as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-bus objects. These new objects can enable rapid access and preservation of wide-buses, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

FinFET cell architecture with power traces

Granted: June 27, 2017
Patent Number: 9691764
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of…

Nanowire or 2D material strips interconnects in an integrated circuit cell

Granted: June 27, 2017
Patent Number: 9691768
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the…

Signal reconstruction in sequential logic circuitry

Granted: June 20, 2017
Patent Number: 9684746
A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on…

Isolation of IP units during emulation of a system on a chip

Granted: June 20, 2017
Patent Number: 9684755
A host system receives a description of a design under test (DUT) that includes multiple IP units and is to be emulated by an emulator. The host system compiles the description of the DUT, which includes synthesizing the description, partitioning the DUT, and mapping the partitions to FPGAs included in the emulator that will emulate the DUT. Each IP unit is part of a single partition or partitioned into multiple partitions and mapped to a different set of FPGAs. The host system…