Synopsys Patent Grants

Method for managing design files shared by multiple users and system thereof

Granted: February 21, 2017
Patent Number: 9575986
A method for managing design files shared by multiple users is provided. A plurality of design files are stored in a design library. A lock table is moved to a memory of a first computer when information of the lock table indicates that the design files were locked by a first process corresponding to a first user, wherein the memory is only accessible to performance of the first process. The lock table is moved from the memory to a common memory of the first computer when one design file…

Lithography aware leakage analysis

Granted: February 21, 2017
Patent Number: 9576098
A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the…

Identifying failure indicating scan test cells of a circuit-under-test

Granted: February 14, 2017
Patent Number: 9568550
A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at…

Processor branch cache with secondary branches

Granted: February 14, 2017
Patent Number: 9569220
A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch…

Delay-locked loop arrangement and method for operating a delay-locked loop circuit

Granted: February 14, 2017
Patent Number: 9571080
Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode…

Early content engine receiver synchronization

Granted: February 14, 2017
Patent Number: 9571473
An HDCP receiver device that receives frames from an HDCP transmitter device. The receiver device has a frame counter that is updated for each frame that is received from the transmitter device and that includes encrypted content, while the receiver device is in a pre-authorization mode. During the pre-authorization mode, the receiver device does not decrypt any received frame bearing encrypted content. While the receiver device waits to transition from the pre-authorization mode to a…

Memory tamper detection

Granted: February 7, 2017
Patent Number: 9563577
A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor. by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one implementation, each of the memory blocks has an authentication code, and the accessing of the memory blocks is disabled by disabling the untrusted…

Retiming a design for efficient parallel simulation

Granted: January 31, 2017
Patent Number: 9558306
An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that…

Determining a user-specified location in a graphical user interface of an electronic design automation tool

Granted: January 24, 2017
Patent Number: 9552450
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in _a circuit design layout in response to modifying the…

NVM device using FN tunneling with parallel powered source and drain

Granted: January 24, 2017
Patent Number: 9553207
A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The…

Efficient event detection

Granted: January 17, 2017
Patent Number: 9547040
Embodiments relate to the emulation of circuits, and detecting an event in a plurality of signals in an emulated circuit. A host system incorporates global event detection logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated global event detection logic. The global event detection logic divides one clock cycle of the DUT into multiple time periods. During each time period of the clock cycle, the emulator selects a different subset of signals from…

Self-timed user-extension instructions for a processing device

Granted: January 17, 2017
Patent Number: 9547493
A processor for executing configurable instructions and a method of configuring the processor are disclosed. In one embodiment, the processor includes (i) a processor core to execute preconfigured instructions and (ii) a processor core extension to execute user-defined extension instructions that are configurable instructions. The user-defined extension instructions may include an autonomous instruction with varying execution cycles based on source data and an operation performed. The…

System and method for viewing and modifying configurable RTL modules

Granted: January 17, 2017
Patent Number: 9547735
A configurable module editor and viewer (CMVE) reads the RTL description of a configurable module keeping track of all possible configuration options. Configuration options include pre-processor macros that are normally removed by RTL parsers. The CMVE allows users to view multiple configurations simultaneously. The CMVE assists users in editing the configurable module by presenting a simplified view of interest, while automatically propagating changes and maintaining consistency in the…

Placing and routing debugging logic

Granted: January 17, 2017
Patent Number: 9547739
Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more…

Methods for fabricating high-density integrated circuit devices

Granted: January 17, 2017
Patent Number: 9547740
An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an…

Periodic signal measurement using statistical sampling

Granted: January 10, 2017
Patent Number: 9541591
A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random…

Automatic control system and method for a true random number generator

Granted: January 10, 2017
Patent Number: 9542156
A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed, and a controller coupled to the true random number generator and the pseudo random number generator to (1) generate a new true random number concurrently…

Constraint memory node identification in sequential logic

Granted: January 10, 2017
Patent Number: 9542514
A method of identifying memory nodes includes reading a netlist of the design. For a sequential cell of the design, constraint arcs between constraint and related pins can be extracted. For each constraint arc, an original vector set including initialization waveforms can be generated. A plurality of simulations can be run using a plurality of vector sets to generate a plurality of node sets. Each simulation generates a corresponding node set that toggles based on waveforms provided by a…

Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations

Granted: January 10, 2017
Patent Number: 9542998
A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. The transient voltage collapse circuit provides the first reference voltage to the SRAM via a voltage supply line. The transient voltage collapse circuit maintains the voltage supply line at a first voltage level during a power save mode of the SRAM. The transient…

Executing a hardware simulation and verification solution

Granted: January 3, 2017
Patent Number: 9536027
One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a…