Synopsys Patent Grants

Hardware accelerator test harness generation

Granted: June 27, 2017
Patent Number: 9690630
System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware…

Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design

Granted: June 27, 2017
Patent Number: 9690890
Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-buses as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-bus objects. These new objects can enable rapid access and preservation of wide-buses, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

FinFET cell architecture with power traces

Granted: June 27, 2017
Patent Number: 9691764
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of…

Nanowire or 2D material strips interconnects in an integrated circuit cell

Granted: June 27, 2017
Patent Number: 9691768
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the…

Isolated debugging in an FPGA based emulation environment

Granted: June 20, 2017
Patent Number: 9684743
For a design under test (DUT) that is to be emulated, a host system partitions the DUT into multiple partitions and maps each partition to an FPGA of an emulator which will emulate the partition. The host system stores information describing to which FPGAs each component of the DUT has been mapped. Additionally, mapped to each FPGA is trace and injection logic that traces signals exchanged by the FPGA with other FPGAs during emulation of the DUT. After the emulation of the DUT is…

Signal reconstruction in sequential logic circuitry

Granted: June 20, 2017
Patent Number: 9684746
A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on…

Isolation of IP units during emulation of a system on a chip

Granted: June 20, 2017
Patent Number: 9684755
A host system receives a description of a design under test (DUT) that includes multiple IP units and is to be emulated by an emulator. The host system compiles the description of the DUT, which includes synthesizing the description, partitioning the DUT, and mapping the partitions to FPGAs included in the emulator that will emulate the DUT. Each IP unit is part of a single partition or partitioned into multiple partitions and mapped to a different set of FPGAs. The host system…

Method and apparatus for process window modeling

Granted: June 13, 2017
Patent Number: 9679086
A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the…

Quality of results system

Granted: June 6, 2017
Patent Number: 9672317
Method and System for determining a next task in an Electronic Design Automation Flow, computer system and computer program product. One or more parsers configurable to identify one or more associated pre-defined data characteristics may be executed by a processor on a task output. Selected values obtained from the parser execution may be used to make a decision about the appropriate next action to be performed in the EDA flow. Selected values may provide suggestions or decisions about…

Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratios

Granted: May 30, 2017
Patent Number: 9665679
A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method…

Method for ranking fault-test pairs based on waveform statistics in a mutation-based test program evaluation system

Granted: May 23, 2017
Patent Number: 9658947
Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a…

X-propagation in emulation

Granted: May 23, 2017
Patent Number: 9659118
Embodiments relate to the emulation of circuits, and representation of unknown states of signals. A disclosed system (and method and computer program product) includes an emulation environment to convert a digital signal of a DUT in a form capable of representing an unknown state. In addition, the disclosed system converts digital logic circuits such as Boolean logic, flip flops, latches, and memory circuits to be operable with signals having unknown states. Thus, an unknown state of a…

Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design

Granted: May 16, 2017
Patent Number: 9652573
Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-gates as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-gate objects. These new objects can enable rapid access and preservation of wide-gates, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Image processing method

Granted: May 16, 2017
Patent Number: 9652889
A computer-implemented image processing technique for selectively recovering the features of an original CAD model after the original CAD model has been converted to a digitized image and a new CAD model generated from the digitized image. The original boundary representation provides a template to transform the representation through processing under governance of a programmed processor so as to recover accuracy and reintroduce feature edges and feature corners as well as other detailed…

3D resist profile aware etch-bias model

Granted: May 9, 2017
Patent Number: 9646127
Systems and techniques for using a three-dimension (3D) resist profile aware etch-bias model are described. A 3D resist profile aware etch-bias model can be calibrated based on empirical data. Next, the 3D resist profile aware etch-bias model can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.

Notch detection and correction in mask design data

Granted: May 9, 2017
Patent Number: 9646129
Mask data is analyzed for the presence of a notch. A notch candidate on a polygon boundary of mask data is defined as a plurality of line segments that includes an initial line segment, a final line segment and at least two line segments therebetween. The initial and final line segments define adjacent edges of the notch candidate. A direction of each line segment is a direction of travel from the initial line segment to the final line segment.

Two-way parity error detection for advanced encryption standard engines

Granted: May 9, 2017
Patent Number: 9646175
A method of improving the operation of a processor executing a cryptographic process, by automatically detecting faults during both encryption and decryption operations by the cryptographic process, comprises segmenting the data to be encrypted and encrypting the data segments using a complex non-linear algorithm that can lead to faults; computing an output parity bit from a selected step of the algorithm for a selected data segment, based on the input value of that segment; comparing…

N-channel and P-channel end-to-end finFET cell architecture

Granted: May 9, 2017
Patent Number: 9646966
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a…

Network-based testing service and method of testing in a network

Granted: May 2, 2017
Patent Number: 9639456
A network-based testing method and service integrated with a tool that publishes one or more tagged test cases with tags being executable to reproduce a sequence of events for a system under test, SUT, caused by an original test case. The method is performed in a network and is intended for testing software or hardware by first creating an original test case for a system under test, SUT, and performing a sequence of events for the original test case for testing it. The tested case is…

Goal-based cell partitioning in the presence of obstacles

Granted: May 2, 2017
Patent Number: 9639648
Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions.