Synopsys Patent Grants

Determining slack estimates for multiple instances of a cell in a hierarchical circuit design

Granted: September 5, 2017
Patent Number: 9754069
Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of…

Path-based floorplan analysis

Granted: September 5, 2017
Patent Number: 9754070
Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.

Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs

Granted: August 29, 2017
Patent Number: 9747403
A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG…

Buffer chain management for alleviating routing congestion

Granted: August 29, 2017
Patent Number: 9747405
Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage,…

Spine routing with multiple main spines

Granted: August 29, 2017
Patent Number: 9747406
A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire…

Categorized stitching guidance for triple-patterning technology

Granted: August 29, 2017
Patent Number: 9747407
A computer-implemented method for validating a design is disclosed. The method includes receiving, with the computer, the design, where the design is printable using a multiple-patterning process when the computer is invoked, and where the design includes a plurality of shapes and at least one conflict preventing decomposition of the design into a plurality of multiple-patterning masks. The method also includes forming a subset of the shapes, the subset including the shapes associated…

Virtual hierarchical layer patterning

Granted: August 22, 2017
Patent Number: 9740811
Identifying the interactions of a selected cell across a hierarchical diagram of an integrated circuit and mapping the ways in which the cell can interact with other structures in the hierarchy reduces the computational load for design rule checking (DRC) and design rules for manufacturing (DRM). To this end, a cell and multiple instances of the cell are identified within hierarchical design levels of the chip. The interactions between the cell and other cells within the hierarchy are…

Virtual cell model geometry compression

Granted: August 22, 2017
Patent Number: 9740812
Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of…

Circuit skew compensation trigger system

Granted: August 22, 2017
Patent Number: 9742406
A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.

Method and apparatus for cipher detection

Granted: August 22, 2017
Patent Number: 9742438
An embodiment of a method and apparatus for ciphering data. Data is provided for ciphering. The data is ciphered in a plurality of steps. For each step, determining an encoding for error detection of the data being processed within the step. Determining an output error detection encoding for the step. Processing data of the round to provide output error detection encoding. Then, verifying the encoding against a determined output error detection encoding. If the output error detection…

2D material super capacitors

Granted: August 15, 2017
Patent Number: 9735227
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide.…

Parameter extraction of DFT

Granted: August 8, 2017
Patent Number: 9727675
Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.

Graphical view and debug for coverage-point negative hint

Granted: August 8, 2017
Patent Number: 9727678
The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in…

Method and apparatus for floating or applying voltage to a well of an integrated circuit

Granted: August 8, 2017
Patent Number: 9728528
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the…

Area-delay-power efficient multibit flip-flop

Granted: August 8, 2017
Patent Number: 9729128
A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local…

Information theoretic caching for dynamic problem generation in constraint solving

Granted: August 1, 2017
Patent Number: 9720792
Computer-implemented techniques are disclosed for verifying circuit designs using dynamic problem generation. A device under test (DUT) is modeled as part of a test bench where the test bench is a random process. A set of constraints is solved to generate stimuli for the DUT. Problem generation is repeated numerous times throughout a verification process with problems and sub-problems being generated and solved. When a problem is solved, the problem structure can be stored in a cache.…

Method for wire widening in circuit routing system

Granted: August 1, 2017
Patent Number: 9721056
A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in…

System and method for netlist clock domain crossing verification

Granted: August 1, 2017
Patent Number: 9721057
A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The…

System and method for reactive initialization based formal verification of electronic logic design

Granted: August 1, 2017
Patent Number: 9721058
A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to…

Protection scheme for embedded code

Granted: July 25, 2017
Patent Number: 9715463
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a…