Performing hardware description language transformations
Granted: December 26, 2023
Patent Number:
11853665
Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be…
Machine-learning enhanced compiler
Granted: December 26, 2023
Patent Number:
11853662
A method includes storing a base model generated using base data and receiving training data generated by compiling circuit designs. The method also includes generating, using the training data, a tuned model and generating, using the training data and the base data, a hybrid model. The method further includes receiving a selected cost function and biasing the base model, the tuned model, and the hybrid model using the selected cost function.
Enriched auto command feature for I3C host controller
Granted: December 26, 2023
Patent Number:
11853236
A device includes a memory, a plurality of registers, a multiplexer/demultiplexer circuit, and a controller circuit. The memory stores a plurality of pages of pointers and a table of commands. The plurality of registers store information about a plurality of target devices. The multiplexer/demultiplexer circuit selects (i) information from a register of the plurality of registers based on a request received from a target device of the plurality of target devices, (ii) a page from the…
Interference reducing passive transmission line receiver
Granted: December 19, 2023
Patent Number:
11848676
The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching…
Integrated circuit design using multi-bit combinational cells
Granted: December 19, 2023
Patent Number:
11847396
Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell…
Automated determinaton of failure mode distribution
Granted: December 12, 2023
Patent Number:
11842134
A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a…
Multi-cycle power analysis of integrated circuit designs
Granted: December 12, 2023
Patent Number:
11842132
A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with…
Machine learning based parasitic estimation for an integrated circuit chip design
Granted: December 5, 2023
Patent Number:
11836435
Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of…
CFET architecture for balancing logic library and SRAM bitcell
Granted: December 5, 2023
Patent Number:
11837280
The independent claims of the present disclosure signify a concise description of embodiments. An electronic structure based on complementary-field effect transistor (CFET) architecture is disclosed. The electronic structure comprises an n-channel metal-oxide-semiconductior (NMOS) gate-all-around (GAA) channel in a first layer, and p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer. The PMOS GAA channel is wider compared to the NMOS GAA channel. The first layer is…
Machine learning-based prediction of metrics at early-stage circuit design
Granted: December 5, 2023
Patent Number:
11836641
When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML)…
Memory instance reconfiguration using super leaf cells
Granted: December 5, 2023
Patent Number:
11836433
A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected…
Engineering change orders with consideration of adversely affected constraints
Granted: December 5, 2023
Patent Number:
11836425
In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related…
Automatic global clock tree synthesis
Granted: December 5, 2023
Patent Number:
11836000
A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second…
System and method for automatically capturing source code and associated artifacts for static analysis
Granted: November 28, 2023
Patent Number:
11829751
This disclosure describes a system and method of automatically capturing source code and associated artifacts for static analysis. A method includes receiving a current state of a project that includes a set of files in a directory to be captured for analysis and a current capture status of individual files of the set of files, determining a plan including a sequence of actions in response to the current state of the project, and executing the sequence of actions to capture each of the…
Guided power grid augmentation system and method
Granted: November 28, 2023
Patent Number:
11829698
A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum…
Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR)
Granted: November 28, 2023
Patent Number:
11829692
Training data may be collected based on a set of test-case configurations for each integrated circuit (IC) design in a set of IC designs. The training data may include a set of features extracted from each IC design, and a count of test cycles required for achieving a target test coverage for each test-case configuration. A machine learning (ML) model may be trained using the training data to obtain a trained ML model. The trained ML model may be used to predict a set of ranked test-case…
Clock multiplexer circuitry with glitch reduction
Granted: November 21, 2023
Patent Number:
11824539
Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and…
Dose information generation and communication for lithography manufacturing systems
Granted: November 21, 2023
Patent Number:
11822232
A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask…
Automatic channel identification of high-bandwidth memory channels for auto-routing
Granted: November 14, 2023
Patent Number:
11816407
Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method…
Strongly connected component (SCC) graph representation for interactive analysis of overlapping loops in emulation and prototyping
Granted: November 14, 2023
Patent Number:
11816409
Embodiments relate to a system and method for analyzing strongly connected components (SCCs) in a design of an integrated circuit. In one embodiment, a design of an integrated circuit is received, and a set of loops are identified in the received design. Based on the identified loops, one or more SCCs are determined. Each SCC includes multiple loops having shared paths. For instance, an SCC includes a first loop having a first set of nodes connected via a first set of paths and a second…
