Volterra Semiconductor Patent Applications

FERRITE INDUCTORS FOR LOW-HEIGHT AND ASSOCIATED METHODS

Granted: August 20, 2015
Application Number: 20150235754
A low-height coupled inductor having length, width, and height includes a composite magnetic core including: (1) first and second magnetic plates separated from each other in the height direction, and (2) a plurality of coupling teeth connecting the first and second magnetic plates in the height direction. The plurality of coupling teeth are formed of magnetic material having a lower magnetic permeability than magnetic material forming the first and second magnetic plates. The low-height…

Coupled Inductors With Non-Uniform Winding Terminal Distributions

Granted: September 18, 2014
Application Number: 20140266086
A coupled inductor includes a ladder magnetic core including two opposing rails extending in a lengthwise direction and joined by a plurality of rungs. The coupled inductor further includes a respective winding wound around each of the plurality of rungs. The plurality of rungs are divided into at least two groups of rungs, and a lengthwise separation distance between adjacent rungs in each group of rungs is less than a lengthwise separation distance between adjacent rungs of different…

Voltage Regulators with Load-Dependent Bias

Granted: September 18, 2014
Application Number: 20140266091
This document describes systems and techniques related to voltage regulators. The subject matter of this document can be embodied in a method that includes measuring an output current of a switching regulator. The switching regulator includes a high-side transistor and a low side-transistor wherein the high-side transistor and the low-side transistor are driven using a first gate voltage and a second, different gate voltage, respectively. The method also includes adjusting a…

Voltage Regulators with Multiple Transistors

Granted: September 18, 2014
Application Number: 20140266113
A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device…

Voltage Regulators with Kickback Protection

Granted: September 18, 2014
Application Number: 20140266130
The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the…

Method For Making Magnetic Components With M-Phase Coupling, And Related Inductor Structures

Granted: September 4, 2014
Application Number: 20140247104
An M phase coupled inductor includes a magnetic core including a first end magnetic element, a second end magnetic element, and M legs disposed between and connecting the first and second end magnetic elements. M is an integer greater than one. The coupled inductor further includes M windings, where each winding has a substantially rectangular cross section. Each one of the M windings is at least partially wound about a respective leg.

LOW PROFILE INDUCTORS FOR HIGH DENSITY CIRCUIT BOARDS

Granted: July 17, 2014
Application Number: 20140198461
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height…

LATERAL DOUBLE-DIFFUSED MOSFET

Granted: June 5, 2014
Application Number: 20140151800
A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a…

Integrated Circuits Including Magnetic Devices, And Associated Methods

Granted: June 5, 2014
Application Number: 20140152350
An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second…

MULTI-TURN INDUCTORS

Granted: May 29, 2014
Application Number: 20140145688
A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core…

Vertical Gate LDMOS Device

Granted: May 29, 2014
Application Number: 20140147979
A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a…

Method of Fabricating Power Transistor with Protected Channel

Granted: May 15, 2014
Application Number: 20140134834
A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an…

FAULT-REJECTING MIXER AND APPLICATIONS

Granted: May 8, 2014
Application Number: 20140125298
Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.

LOW PROFILE INDUCTORS FOR HIGH DENSITY CIRCUIT BOARDS

Granted: May 1, 2014
Application Number: 20140118965
An inductor includes a core formed of a magnetic material and a foil winding wound at least partially around or through at least a portion of the core. A first end of the winding extends away from the core to form an extended output tongue configured and arranged to supplement or serve as a substitute for a printed circuit board foil trace. A second end of the winding forms a solder tab. At least a portion of the extended output tongue and the solder tab are formed at a same height…

MAXIMUM POWER POINT CONTROLLER TRANSISTOR DRIVING CIRCUITRY AND ASSOCIATED METHODS

Granted: April 17, 2014
Application Number: 20140103723
An electric power system includes a string of N maximum power point tracking (MPPT) controllers having output ports electrically coupled in series, where N is an integer greater than one. At least one of the N MPPT controllers includes respective transistor driver circuitry powered from a power supply rail of an adjacent one of the N MPPT controllers of the string. Another MPPT controller includes an n-channel field effect freewheeling transistor electrically coupled across an output…

Systems And Methods For Controlling Maximum Power Point Tracking Controllers

Granted: April 17, 2014
Application Number: 20140103891
A method for operating a maximum power point tracking (MPPT) controller including a switching circuit adapted to transfer power between an input port and an output port includes the steps of: (a) in a first operating mode of the MPPT controller, causing a first switching device of the switching circuit to operate at a fixed duty cycle; and (b) in a second operating mode of the MPPT controller, causing a control switching device of the switching circuit to repeatedly switch between its…

SCALABLE MAXIMUM POWER POINT TRACKING CONTROLLERS AND ASSOCIATED METHODS

Granted: April 17, 2014
Application Number: 20140103892
A scalable maximum power point tracking (MPPT) controller includes an input and an output port, a switching circuit adapted to transfer power from the input port to the output port, and a controller core. The controller core is adapted to (a) control the switching circuit to maximize an amount of power extracted from a photovoltaic device electrically coupled to the input port, and (b) set one or more parameters of the MPPT controller based at least in part on a configuration code…

Maximum Power Point Tracking Controllers And Associated Systems And Methods

Granted: April 17, 2014
Application Number: 20140103894
A maximum power point tracking controller includes an input port for electrically coupling to an electric power source, an output port for electrically coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control switching of the control switching device to regulate a…

Two Step Poly Etch LDMOS Gate Formation

Granted: March 27, 2014
Application Number: 20140087531
A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.

Methods and Apparatus for LDMOS Transistors

Granted: September 12, 2013
Application Number: 20130234249
An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth…