Techniques for Boundary Scan Testing Using Transmitters and Receivers
Granted: October 14, 2010
Application Number:
20100262877
A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller
Granted: October 7, 2010
Application Number:
20100257290
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal…
INTERACTIVE SIMPLIFICATION OF SCHEMATIC DIAGRAM OF INTEGRATED CIRCUIT DESIGN
Granted: September 30, 2010
Application Number:
20100251201
The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a…
PROCESSORS AND COMPILING METHODS FOR PROCESSORS
Granted: September 30, 2010
Application Number:
20100251229
A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first…
Methods and Apparatus for Video Decoding
Granted: September 23, 2010
Application Number:
20100238999
Techniques for performing the processing of blocks of video in multiple stages. Each stage is executed for blocks of data in the frame that need to go through that stage, based on the coding type, before moving to the next stage. This order of execution allows blocks of data to be processed in a nonsequential order, unless the blocks need to go through the same processing stages. Multiple processing elements (PEs) operating in SIMD mode executing the same task and operating on different…
Techniques for Providing Calibrated On-Chip Termination Impedance
Granted: September 9, 2010
Application Number:
20100225349
Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to…
METHOD AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES
Granted: September 2, 2010
Application Number:
20100223445
A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.
Multi-protocol channel-aggregated configurable transceiver in an integrated circuit
Granted: August 26, 2010
Application Number:
20100215086
Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry…
FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC
Granted: August 19, 2010
Application Number:
20100207659
A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA…
NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES
Granted: July 15, 2010
Application Number:
20100177560
A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment,…
Digital Calibration Techniques for Segmented Capacitor Arrays
Granted: June 17, 2010
Application Number:
20100148881
An apparatus includes phase detection circuitry that generates control signals in response to an input clock signal and a feedback clock signal. The apparatus also includes a clock signal generation circuit that includes fine and coarse capacitors. The clock signal generation circuit changes a capacitance of the capacitors that are affecting the output clock signal in response to a change in the control signals. The apparatus also includes measurement circuitry that determines a…
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Granted: May 13, 2010
Application Number:
20100121899
Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex…
Techniques For Providing Option Conductors to Connect Components in an Oscillator Circuit
Granted: April 15, 2010
Application Number:
20100090774
An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES
Granted: April 1, 2010
Application Number:
20100082891
A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
Techniques For Digital Loop Filters
Granted: March 25, 2010
Application Number:
20100073054
A digital loop filter includes a fine control circuit and a coarse control circuit. The fine control circuit adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal. The coarse control circuit adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal. The second phase…
PHASE SHIFT CIRCUIT WITH LOWER INTRINSIC DELAY
Granted: March 25, 2010
Application Number:
20100073060
A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first…
Techniques For Generating Fractional Clock Signals
Granted: March 25, 2010
Application Number:
20100073094
A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided…
MULTI-ROW BLOCK SUPPORTING ROW LEVEL REDUNDANCY IN A PLD
Granted: March 11, 2010
Application Number:
20100060309
In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections when a fault occurs. The redundant internal logic connections extend through a row, linking the row above a defective row with a row below the defective row. Elements in a multi-row block are configurable to perform a default function and a function of an element in a neighboring row, if the…
DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION
Granted: March 11, 2010
Application Number:
20100061166
In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES
Granted: March 4, 2010
Application Number:
20100058099
High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling…
