Distributed multi-die protocol application interface
Granted: November 19, 2024
Patent Number:
12147377
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels.…
Interface bridge between integrated circuit die
Granted: November 5, 2024
Patent Number:
12135667
An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip…
Integrated circuit device with embedded programmable logic
Granted: November 5, 2024
Patent Number:
12135660
Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may…
Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same
Granted: October 22, 2024
Patent Number:
12125768
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an…
Computing system for generating customized health form based on clinical data
Granted: October 8, 2024
Patent Number:
12112124
A computing system that facilitates generating customized health forms for a patient is disclosed herein. Subsequent to receiving a patient identifier from a client computing device, a server electronic health records application (EHR) transmits clinical data assigned to the patient identifier to a server health form application. Based on the clinical data assigned to the patient, the server health form application generates a customized health form for the patient using form data. The…
Package antenna and radar assembly package
Granted: September 10, 2024
Patent Number:
12087999
The present disclosure provides a package antenna and a radar assembly package. The package antenna includes a first antenna and a second antenna adjacent to the first antenna. Directivity of electromagnetic wave from the package antenna is achieved through the cancelation of radiation fields from the first and second antennas.
Systems and methods for detecting and configuring lanes in a circuit system
Granted: September 10, 2024
Patent Number:
12087381
An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the…
Multichip package with protocol-configurable data paths
Granted: September 10, 2024
Patent Number:
12086088
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…
Systems and methods for electronically scanned array antennas
Granted: September 3, 2024
Patent Number:
12081247
An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, mixer circuits, and antennas. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are…
Circuit and method for link verification by HDCP receiver
Granted: August 27, 2024
Patent Number:
12075114
A method for an audiovisual receiver to request an audiovisual transmitter to reset a communication link includes requesting the reset when the audiovisual receiver determines that the communication link is unlocked. The communication is determined to be unlocked when the active geometry of successive audiovisual frames transmitted from the transmitter to the receiver is determined by the receiver to be inconsistent. The communication is also determined to be unlocked when the interval…
Orthogonal multi-phase scheduling circuitry
Granted: August 6, 2024
Patent Number:
12056065
An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase…
Automatic gain control method, sensor, and radio device
Granted: July 23, 2024
Patent Number:
12047209
An automatic gain control method, sensor (700), and radio device (900); by means of using the saturation information of a test echo unit to adjust the gain coefficient of a transmitting and receiving link, it is ensured that the received signal power used for target detection is located within a rated threshold range, further improving the accuracy of sensor (700) target detection, and avoiding defects such as missed detection, false detection, and even blindness.
Techniques for clock signal transmission in integrated circuits and interposers
Granted: July 2, 2024
Patent Number:
12026008
An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of…
Computing system for cross-site request forgery attack protection
Granted: June 18, 2024
Patent Number:
12015638
A server agent application receives a uniform resource locator (URL) from a client agent application, the URL including an identifier for a graphical resource. The server agent application determines, based upon the URL, that a third-party application is to provide the graphical resource. The server agent application causes an intermediate application to be launched. The intermediate application requests a webpage from the third-party application, the webpage including a security token…
Low-latency optical connection for CXL for a server CPU
Granted: June 11, 2024
Patent Number:
12007929
A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one…
Techniques for generating a PAM eye diagram in a receiver
Granted: June 4, 2024
Patent Number:
12003352
A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a…
Methods and systems for visualizing patient population data
Granted: May 21, 2024
Patent Number:
11990213
Technologies pertaining to assigning patients to patient populations and graphically indicating that the patients have been assigned to the patient populations are described herein. A graphical user interface includes interactive elements that are configured to indicate to a healthcare worker that a patient has been assigned to a population, and further to depict proposed actions based upon the patient being assigned to the population.
Network functions virtualization platforms with function chaining capabilities
Granted: April 16, 2024
Patent Number:
11960921
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine…
Accelerator architecture on a programmable platform
Granted: October 24, 2023
Patent Number:
11797473
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
Network functions virtualization platforms with function chaining capabilities
Granted: June 27, 2023
Patent Number:
11687358
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine…
