Compute-in-memory systems and methods
Granted: January 28, 2025
Patent Number:
12210873
An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.
Joint channel filtering and crest factor reduction architecture
Granted: January 21, 2025
Patent Number:
12206447
A signal processing device includes a filter, configured to receive first data representing a signal for wireless transmission, modify the first data in a filter operation, and output second data as the modified first data; a peak detector, configured to detect third data representing a peak of the signal, wherein the third data are a subset of the first data; a signal canceller, configured to receive the third data and to generate fourth data representing a cancellation signal…
Flushing cache lines involving persistent memory
Granted: January 21, 2025
Patent Number:
12204441
A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.
Rank-based dot product circuitry
Granted: January 14, 2025
Patent Number:
12197888
Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper…
Floating-point decomposition circuitry with dynamic precision
Granted: January 14, 2025
Patent Number:
12197887
Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point…
At-speed burst sampling for user registers
Granted: January 14, 2025
Patent Number:
12197360
Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the…
Seemingly monolithic interface between separate integrated circuit die
Granted: January 7, 2025
Patent Number:
12191893
A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the…
Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device
Granted: December 31, 2024
Patent Number:
12183412
An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.
Systems and methods for aligning received data
Granted: December 31, 2024
Patent Number:
12182050
The present application is directed to an electronic device that includes a receiver configured to receive data from a second electronic device. The data includes a plurality of blocks, and each block of the plurality of blocks comprises a sync header. The receiver is also configured to align the data by performing 2 to 1 multiplexing and output the aligned data.
Micro-network-on-chip and microsector infrastructure
Granted: December 10, 2024
Patent Number:
12164462
Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to…
Modular periphery tile for integrated circuit device
Granted: November 26, 2024
Patent Number:
12153866
Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from…
Distributed multi-die protocol application interface
Granted: November 19, 2024
Patent Number:
12147377
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels.…
Interface bridge between integrated circuit die
Granted: November 5, 2024
Patent Number:
12135667
An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip…
Integrated circuit device with embedded programmable logic
Granted: November 5, 2024
Patent Number:
12135660
Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may…
Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same
Granted: October 22, 2024
Patent Number:
12125768
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an…
Computing system for generating customized health form based on clinical data
Granted: October 8, 2024
Patent Number:
12112124
A computing system that facilitates generating customized health forms for a patient is disclosed herein. Subsequent to receiving a patient identifier from a client computing device, a server electronic health records application (EHR) transmits clinical data assigned to the patient identifier to a server health form application. Based on the clinical data assigned to the patient, the server health form application generates a customized health form for the patient using form data. The…
Package antenna and radar assembly package
Granted: September 10, 2024
Patent Number:
12087999
The present disclosure provides a package antenna and a radar assembly package. The package antenna includes a first antenna and a second antenna adjacent to the first antenna. Directivity of electromagnetic wave from the package antenna is achieved through the cancelation of radiation fields from the first and second antennas.
Systems and methods for detecting and configuring lanes in a circuit system
Granted: September 10, 2024
Patent Number:
12087381
An electronic circuit system includes a main device that generates first and second strobe signals and a clock signal, a first peripheral device that uses the first strobe signal to generate a first output signal in a first lane in response to the clock signal, and a second peripheral device that uses the second strobe signal to generate a second output signal in a second lane in response to the clock signal. The main device determines if the first peripheral device is coupled to the…
Multichip package with protocol-configurable data paths
Granted: September 10, 2024
Patent Number:
12086088
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…
Systems and methods for electronically scanned array antennas
Granted: September 3, 2024
Patent Number:
12081247
An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, mixer circuits, and antennas. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are…
