Altera Patent Grants

Techniques for enabling and disabling transistor legs in an output driver circuit

Granted: October 17, 2017
Patent Number: 9793888
An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The control circuit enables the first transistor leg to generate an output signal at the output pad and disables the second transistor leg during a first phase of a cycle. The control circuit…

Differential input buffer circuits and methods

Granted: October 17, 2017
Patent Number: 9793893
A termination circuit includes a first transistor coupled to a first pad, a first resistor coupled between the first transistor and a second pad, and an operational amplifier circuit. The termination circuit provides termination impedance to input signals received at the first and second pads. The first transistor generates a first common mode voltage of the input signals at a first node between the first resistor and the first transistor in response to an output signal of the…

Resource-saving circuit structures for deeply pipelined systolic finite impulse response filters

Granted: October 10, 2017
Patent Number: 9787290
Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to…

Methods and devices for reducing clock skew in bidirectional clock trees

Granted: October 10, 2017
Patent Number: 9787311
The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch…

Integrated circuit calibration system using general purpose processors

Granted: October 3, 2017
Patent Number: 9778312
In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the…

Integrated circuit package substrates having a common die dependent region and methods for designing the same

Granted: October 3, 2017
Patent Number: 9780040
Techniques for designing integrated circuit (IC) package substrates are provided. One of the provided techniques include routing a first set of interconnects in a first region of an IC package substrate based on a first routing template and routing a second set of interconnects in a second region of the IC package substrate based on a second routing template. The first routing template is associated with output pins on the IC package substrate while the second routing template is…

Apparatus for automatically configured interface and associated methods

Granted: October 3, 2017
Patent Number: 9780789
An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value.

Methods and apparatuses for offsetting aging in pass transistors

Granted: October 3, 2017
Patent Number: 9780793
Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process is essentially nullified.

Low-skew channel bonding using oversampling

Granted: September 26, 2017
Patent Number: 9772649
In accordance with an embodiment of the invention, higher-speed outgoing data paths are used to transmit oversampled data signals, and corresponding slower-speed return data paths are used to receive return data signals. A channel-bonding control circuit measures the skew between the returned data signals and generates bit-slip and/or word-slip control signals to compensate for the skew. Transmission bit-slip (or, alternatively, clock-slip) circuits slip integer numbers of bits based on…

Techniques for detecting and correcting errors on a ring oscillator

Granted: September 26, 2017
Patent Number: 9774316
A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error…

Low-skew channel bonding using phase-measuring FIFO buffer

Granted: September 26, 2017
Patent Number: 9774478
Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass…

Setting security features of programmable logic devices

Granted: September 19, 2017
Patent Number: 9767321
Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the programmable integrated circuit device with the configuration data or prevent such configuration. Control circuitry…

Memory elements with dynamic pull-up weakening write assist circuitry

Granted: September 19, 2017
Patent Number: 9767892
Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from…

Resistive structure with enhanced thermal dissipation

Granted: September 19, 2017
Patent Number: 9768093
An integrated circuit is provided. The integrated circuit includes a continuous resistor body having first and second distal terminals, and a group of electrically-floating dummy conductors that are formed above the continuous resistor body, and between the first and second distal terminals of the continuous resistor body. Each of the group of dummy conductors is coupled to the continuous resistor body through a respective via structure. The group of dummy conductors serves to dissipate…

Register circuitry with asynchronous system reset

Granted: September 19, 2017
Patent Number: 9768757
Integrated circuits having flip-flops with asynchronous reset capabilities are provided. The flip-flops may be single event upset (SEU) hardened registers implemented using dual-interlocked cell (DICE) latch circuits. A logic gate may be inserted at the data input of each flip-flop. A multiplexer may be inserted at the input of the clock tree that is being used to feed clock signals to each of the flip-flops. Both the logic gate and the multiplexer may receive an asynchronous reset…

Methods for operating configurable storage and processing blocks at double and single data rates

Granted: September 19, 2017
Patent Number: 9768783
Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other…

Transformable logic and routing structures for datapath optimization

Granted: September 19, 2017
Patent Number: 9768784
Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (LUT) circuitry driven using vectored multiplexing circuits. The vectored multiplexing circuits may include a first multiplexer stage controlled by common configuration bits, a second multiplexer stage, and means for connecting either outputs of the first multiplexer stage or…

Compression using mu-law approximation

Granted: September 12, 2017
Patent Number: 9762285
Techniques and mechanisms provide a technique for compression using an approximation of a mu-law algorithm.

Multi-processor integrated circuits

Granted: September 5, 2017
Patent Number: 9753765
An integrated circuit unit and method for synchronizing processing threads running on respective processors are provided. The unit includes an interrupt request controller which is programmable to provide a first desired number of synchronization objects and a second desired number of interrupt request signals for supply to such processors. The controller is operable to direct and interrupt request signals to a chosen processor in dependence upon data received from the processors.

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

Granted: September 5, 2017
Patent Number: 9754065
A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.