Electronic systems for integrated circuits and voltage regulators
Granted: May 6, 2025
Patent Number:
12292752
An electronic system includes first, second, third, and fourth integrated circuit dies. The third integrated circuit die has a first voltage regulator circuit. A supply voltage output of the first voltage regulator circuit is coupled to provide a first supply voltage to a supply voltage input of the first integrated circuit die. The first voltage regulator circuit generates a first power ready signal that indicates when the first supply voltage has reached a first threshold voltage. The…
Radar system and control method therefor
Granted: April 22, 2025
Patent Number:
12282085
A radar system and control method thereof is disclosed. The radar system comprises a plurality of radar units, each comprising: one or more radio frequency (RF) channels configured to receive a reflected signal and then generate an analog input signal according to the reflected signal; and a processing module connected with all the RF channels and configured to sample the analog input signal to obtain a digital signal and perform the first digital signal processing on the digital signal…
Fast fourier transform (FFT) based digital signal processing (DSP) engine
Granted: April 15, 2025
Patent Number:
12278630
A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset…
Radio frequency inverter, transmission line phase shifter, system, chip, and radar sensor
Granted: April 15, 2025
Patent Number:
12278411
A radio frequency (RF) inverter, a transmission line phase shifter, a system, a chip, and a radar sensor are provided. The RF inverter includes an inductance circuit and a first phase adjusting circuit that both are arranged symmetrically along a same symmetry axis. The inductance circuit includes a single-ended signal interface and a differential signal interface. The first phase adjusting circuit includes two controlled switches, and each controlled switch is connected between the…
System-in-package network processors
Granted: April 8, 2025
Patent Number:
12273282
This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
Dynamically scalable timing and power models for programmable logic devices
Granted: April 8, 2025
Patent Number:
12273107
Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new…
Innovative interconnect design for package architecture to improve latency
Granted: April 1, 2025
Patent Number:
12266625
An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The…
Integrated circuit with peek and poke protection circuitry for multi-tenant usage model
Granted: April 1, 2025
Patent Number:
12265772
Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits…
Configurable clock macro circuits and methods
Granted: April 1, 2025
Patent Number:
12265417
An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second…
Circuit systems and methods for reducing power supply voltage droop
Granted: March 18, 2025
Patent Number:
12255648
A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of…
Vector processor architectures
Granted: March 18, 2025
Patent Number:
12254316
The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector…
Voltage regulator circuit systems and methods
Granted: March 18, 2025
Patent Number:
12253870
A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second…
Circuits and methods for detecting decreases in a supply voltage in an integrated circuit
Granted: March 11, 2025
Patent Number:
12249988
An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that…
Debug trace microsectors
Granted: March 11, 2025
Patent Number:
12248021
Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to…
Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same
Granted: February 25, 2025
Patent Number:
12237245
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an…
On-die aging measurements for dynamic timing modeling
Granted: February 4, 2025
Patent Number:
12216150
A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information…
Compute-in-memory systems and methods
Granted: January 28, 2025
Patent Number:
12210873
An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.
Joint channel filtering and crest factor reduction architecture
Granted: January 21, 2025
Patent Number:
12206447
A signal processing device includes a filter, configured to receive first data representing a signal for wireless transmission, modify the first data in a filter operation, and output second data as the modified first data; a peak detector, configured to detect third data representing a peak of the signal, wherein the third data are a subset of the first data; a signal canceller, configured to receive the third data and to generate fourth data representing a cancellation signal…
Flushing cache lines involving persistent memory
Granted: January 21, 2025
Patent Number:
12204441
A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.
Rank-based dot product circuitry
Granted: January 14, 2025
Patent Number:
12197888
Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper…
