DYNAMIC RANDOM-ACCESS MEMORY (DRAM) PHASE TRAINING UPDATE
Granted: February 1, 2024
Application Number:
20240036748
A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the…
DYNAMIC PERFORMANCE ADJUSTMENT
Granted: February 1, 2024
Application Number:
20240037031
A technique for operating a device is disclosed. The technique includes recording log data for the device; analyzing the log data to determine one or more performance settings adjustments to apply to the device; and applying the one or more performance settings adjustments to the device.
DYNAMIC RANDOM-ACCESS MEMORY (DRAM) PHASE TRAINING UPDATE
Granted: February 1, 2024
Application Number:
20240036748
A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the…
MULTI-ACCELERATOR COMPUTE DISPATCH
Granted: January 25, 2024
Application Number:
20240029336
Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such…
MULTI-ACCELERATOR COMPUTE DISPATCH
Granted: January 25, 2024
Application Number:
20240029336
Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such…
DISTRIBUTION OF A WORKLOAD AMONG NODES OF A SYSTEM WITH A NUMA ARCHITECTURE
Granted: January 18, 2024
Application Number:
20240020173
Methods and systems are disclosed for distribution of a workload among nodes of a NUMA architecture. Techniques disclosed include receiving the workload and data batches, the data batches to be processed by the workload. Techniques disclosed further include assigning workload processes to the nodes according to a determined distribution, and, then, executing the workload according to the determined distribution. The determined distribution is selected out of a set of distributions, so…
DISTRIBUTION OF A WORKLOAD AMONG NODES OF A SYSTEM WITH A NUMA ARCHITECTURE
Granted: January 18, 2024
Application Number:
20240020173
Methods and systems are disclosed for distribution of a workload among nodes of a NUMA architecture. Techniques disclosed include receiving the workload and data batches, the data batches to be processed by the workload. Techniques disclosed further include assigning workload processes to the nodes according to a determined distribution, and, then, executing the workload according to the determined distribution. The determined distribution is selected out of a set of distributions, so…
SCHEDULING TRAINING OF AN INTER-CHIPLET INTERFACE
Granted: January 4, 2024
Application Number:
20240004815
Systems and methods are disclosed for scheduling a data link training by a controller. The system and method include receiving an indication that a physical layer of a data link is not transferring data and initiating a training process of the physical layer of the data link in response to the indication that the physical layer of the data link is not transferring data. In one aspect, the indication that the physical layer of a data link is not transferring data is an indication that the…
CHANNEL AND SUB-CHANNEL THROTTLING FOR MEMORY CONTROLLERS
Granted: January 4, 2024
Application Number:
20240005971
An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of…
DROOP MITIGATION FOR AN INTER-CHIPLET INTERFACE
Granted: January 4, 2024
Application Number:
20240004821
Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the…
DEPTH MAP CONSTRUCTION BY CAMERA PHASE DETECTION AND LENS CALIBRATION
Granted: January 4, 2024
Application Number:
20240003680
Techniques for generating a depth map are described. The techniques include obtaining a set of phase difference measurements with a phase detect sensor, and generating a depth map based on the set of phase difference measurements, utilizing a first set of calibration data correlating phase difference measurements with lens defocus data and a second set of calibration data correlating lens positions with object distances.
ENCODED DATA DEPENDENCY MATRIX FOR POWER EFFICIENCY SCHEDULING
Granted: January 4, 2024
Application Number:
20240004657
The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the…
ACCELERATING PREDICATED INSTRUCTION EXECUTION IN VECTOR PROCESSORS
Granted: January 4, 2024
Application Number:
20240004656
Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements…
Intermediate Representation Controller Circuit for Selecting Hardware Compute Units to Process Microcode According to Identified Intermediate Representation Primitives
Granted: January 4, 2024
Application Number:
20240004645
An intermediate representation (IR) controller is described that, for a given intermediate representation (IR) primitive, selects a hardware compute unit of a plurality of hardware compute units. In a non-limiting example, the IR controller receives an input that specifies an IR primitive, a device mask indicating a type of hardware circuitry to be used to process the primitive, and a goal vector specifying a goal in the processing of the primitive. The IR controller also collects data…
DRAM Row Management for Processing in Memory
Granted: January 4, 2024
Application Number:
20240004584
In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second…
PROTOCOL FOR DATA POISONING
Granted: January 4, 2024
Application Number:
20240004583
A random-access memory (RAM) includes a plurality of memory banks, a memory channel interface circuit, and a metadata processing circuit. The memory channel interface circuit couples to a memory channel adapted for coupling to a memory controller. The metadata processing circuit is connected to the memory channel interface circuit and receiving a poison bit sent over the memory channel associated with a write command and write data for the write command. The RAM, responsive to the poison…
EFFICIENT MEMORY POWER CONTROL OPERATIONS
Granted: January 4, 2024
Application Number:
20240004560
A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory…
TECHNIQUES FOR REDUCING PROCESSOR POWER CONSUMPTION
Granted: January 4, 2024
Application Number:
20240004453
Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more…
REST-OF-CHIP POWER OPTIMIZATION THROUGH DATA FABRIC PERFORMANCE STATE MANAGEMENT
Granted: January 4, 2024
Application Number:
20240004444
Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.
PHASE DETECTION TECHNIQUES FOR HALF-SHIELD PHASE-DETECT SENSORS
Granted: January 4, 2024
Application Number:
20240003748
Techniques for performing phase detect operations are described. The techniques include obtaining first measurements with a set of half-shield phase-detect sensors; obtaining second measurements with a set of non-phase detect sensors that are not configured as phase-detect sensor; and determining a phase difference based on the first measurements and the second measurements.
