ACCELERATED PROCESSING DEVICE AND METHOD OF SHARING DATA FOR MACHINE LEARNING
Granted: January 5, 2023
Application Number:
20230004385
A processing device is provided which comprises a plurality of compute units configured to process data, a plurality of arithmetic logic units, instantiated separate from the plurality of compute units, and configured to store the data at the arithmetic logic units and perform calculations using the data and an interconnect network, connecting the arithmetic logic units and configured to provide the arithmetic logic units with shared access to the data for communication between the…
DEMAND BASED PROBE FILTER INITIALIZATION AFTER LOW POWER STATE
Granted: December 29, 2022
Application Number:
20220413586
A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power…
METHOD AND APPARATUS FOR ADJUSTING VIDEO BRIGHTNESS
Granted: December 29, 2022
Application Number:
20220417466
A method and apparatus for adjusting a display includes receiving a video stream. The video stream is analyzed for one or more environmental conditions. Based upon the analysis, a portion of the display is adjusted.
BUFFER MANAGEMENT FOR PLUG-IN ARCHITECTURES IN COMPUTATION GRAPH STRUCTURES
Granted: December 29, 2022
Application Number:
20220417382
A computer vision processing device is provided which comprises memory configured to store data and a processor. The processor is configured to store captured image data in a first buffer and acquire access to the captured image data in the first buffer when the captured image data is available for processing. The processor is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and…
PER-PIXEL VARIABLE RATE SHADING CONTROLS USING STENCIL DATA
Granted: December 29, 2022
Application Number:
20220414950
A disclosed technique includes determining a plurality of per-pixel variable rate shading rates for a plurality of fragments; determining a coarse variable shading rate for a coarse variable rate shading area based on the plurality of per-pixel variable rate shading rates; and shading one or more fragments based on the plurality of fragments and based on the coarse variable shading rate.
RENDER TARGET COMPRESSION SCHEME COMPATIBLE WITH VARIABLE RATE SHADING
Granted: December 29, 2022
Application Number:
20220414939
A disclosed technique includes reading, from a compressed render target, a set of unique color values for a coarse pixel, wherein the coarse pixel includes multiple render target pixels; reading, from the compressed render target, pointers to the unique color values for the coarse pixel; and generating colors for the multiple render target pixels based on the unique color values and the pointers.
PRECISE SHADOWING AND ADJUSTMENT OF ON-DIE TIMERS IN LOW POWER STATES
Granted: December 29, 2022
Application Number:
20220413984
An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an…
PROCESSING DEVICE AND METHOD OF USING A REGISTER CACHE
Granted: December 29, 2022
Application Number:
20220413858
A processing device is provided which comprises memory, a plurality of registers and a processor. the processor is configured to execute a plurality of portions of a program, allocate a number of the registers per portion of the program such that a number of remaining registers are available as a register cache and transfer data between the number of registers, which are allocated per portion of the program, and the register cache. The processor loads data to the allocated registers to…
PROVIDING ATOMICITY FOR COMPLEX OPERATIONS USING NEAR-MEMORY COMPUTING
Granted: December 29, 2022
Application Number:
20220413849
Providing atomicity for complex operations using near-memory computing is disclosed. In an implementation, a complex atomic operation is decomposed into a set of sequential operations that is stored in a near-memory instruction store. A memory controller receives a request from a host execution engine to issue the complex atomic operation and initiates execution of the stored set of sequential operations on a near-memory compute unit. The complex atomic operation may be a user-defined…
EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER
Granted: December 29, 2022
Application Number:
20220413759
A data processor includes a staging buffer, a command queue, a picker, and an arbiter. The staging buffer receives and stores first memory access requests. The command queue stores second memory access requests, each indicating one of a plurality of ranks of a memory system. The picker picks among the first memory access requests in the staging buffer and provides selected ones of the first memory access requests to the command queue. The arbiter selects among the second memory access…
MEMORY CONTROLLER WITH HYBRID DRAM/PERSISTENT MEMORY CHANNEL ARBITRATION
Granted: December 22, 2022
Application Number:
20220405214
A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among…
REDUNDANCY METHOD AND APPARATUS FOR SHADER COLUMN REPAIR
Granted: October 27, 2022
Application Number:
20220343456
Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit…
KERNEL SIZE INDEPENDENT POOLING OPERATIONS
Granted: October 13, 2022
Application Number:
20220327353
Devices, methods, and systems for determining N-dimensional MaxPool or AvgPool for a M-dimensional input array. For each of N dimensions, in order from highest to lowest dimension i: the M dimensional input array is decomposed into 1 dimensional (1D) input arrays in the ith dimension, 1D MaxPool or AvgPool is performed on each of the 1D input arrays in the ith dimension to generate 1D output arrays in the ith dimension, and the M dimensional input array is recomposed from the 1D output…
DATA FABRIC CLOCK SWITCHING
Granted: October 6, 2022
Application Number:
20220317755
A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to…
POST-DEPTH VISIBILITY COLLECTION WITH TWO LEVEL BINNING
Granted: October 6, 2022
Application Number:
20220319091
A method and apparatus of tile rendering of an image for a display in a computer system includes receiving the image in a graphics pipeline of the computer system, the image comprising one or more three dimensional (3D) objects. The image is divided into one or more tiles. A depth test is performed on the one or more tiles, and based upon the depth test, visibility information of the one or more tiles is binned.
EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING
Granted: October 6, 2022
Application Number:
20220317934
A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded…
DRAM COMMAND STREAK EFFICIENCY MANAGEMENT
Granted: October 6, 2022
Application Number:
20220317928
A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a…
ADAPTIVE MEMORY CONSISTENCY IN DISAGGREGATED DATACENTERS
Granted: October 6, 2022
Application Number:
20220317927
A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorized to access. If a notification indicates that more than one requestor is authorized to access…
EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING
Granted: October 6, 2022
Application Number:
20220317924
A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded…
WRITE BANK GROUP MASK DURING ARBITRATION
Granted: October 6, 2022
Application Number:
20220317923
A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a DRAM memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless…
